Matches 1 - 50 out of 552 1 2 3 4 5 6 7 8 9 10 11 12 >
Match Document Document Title
7624321 IEEE 1149.1 and P1500 test interfaces combined circuits and processes  
In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered...
7624320 Apparatus for testing system-on-chip  
A system-on-chip (SoC) test apparatus is disclosed. The system-on-chip (SoC) testing apparatus reduces a test time due to a small amount of overhead in the case of testing an AMBA-based...
7620867 IP core design supporting user-added scan register option  
An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15 , test data output leads 13 , control...
7620866 Test access architecture and method of testing a module in an electronic circuit  
According to an example embodiment of the present invention, there is a test access architecture for testing modules in an electronic circuit. The test access architecture includes a test access...
7620864 Method and apparatus for controlling access to and/or exit from a portion of scan chain  
The present invention provides a method, apparatus and program product for providing controlled access to and/or exit from a portion of a scan chain. The method, apparatus, and program product take...
7617425 Method for at-speed testing of memory interface using scan  
A method and a circuit of testing of a memory interface associated with an embedded memory in a semiconductor circuit involves writing to two memory locations in succession; reading the two memory...
7613971 Semiconductor integrated circuit with delay test circuit, and method for testing semiconductor integrated circuit  
A semiconductor integrated circuit includes an input side flip-flop; a combinational circuit having an input connected with the input side flip-flop; an output side flip-flop connected with an...
7613968 Device and method for JTAG test  
In order to realize a JTAG test of a printed board including a semiconductor device having JTAG test unsupported input/output terminals inside thereof, one device is logically divided into two...
7610536 Select and enable leads connecting IC taps and embedded controller  
A TAP linking module ( 21, 51 ) permits plural TAPs (TAPs 1 - 4 ) to be controlled and accessed from a test bus ( 13 ) via a single TAP interface ( 20 ).
7610535 Boundary scan connector test method capable of fully utilizing test I/O modules  
Read the description file of a PCBA without determining and selecting connectors which might be relevant to boundary scan. The description file of the PCBA determines which pins of the connectors...
7610534 Determining a length of the instruction register of an unidentified device on a scan chain  
Methods and systems are provided for determining a total length of instruction registers. A data shift of a scan chain determines whether each device in the scan chain is an identified device. An...
7607058 Removable and replaceable tap domain selection circuitry  
Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it...
7607057 Test wrapper including integrated scan chain for testing embedded hard macro in an integrated circuit chip  
An apparatus and method are disclosed for testing a hard macro that is embedded in a system on a chip (SOC) that is included in an integrated circuit chip. The SOC includes the hard macro. A logic...
7602729 Slow-fast programming of distributed base stations in a wireless network  
A slow fast programming method for efficient remote field update in distributed base stations overcomes significant fiber propagation delay associated with a remote unit by applying programming...
7600168 Apparatus with programmable scan chains for multiple chip modules and method for programming the same  
An apparatus provided with programmable scan chains includes a scan chain having a scan input port and a scan output port, a plurality of first I/O ports, an input port selector for selecting one...
7596737 System and method for testing state retention circuits  
This invention discloses a system and method for testing a plurality of state retention circuits in an integrated circuit (IC) chip, that comprises a built-in test circuit configured to invoke a...
7596735 Pad unit having a test logic circuit and method of driving a system including the same  
Noise may cause malfunction and reduction of yield in semiconductor devices operating with a low supply voltage, and a logic test is generally performed for testing characteristics of input/output...
7594150 Fault-tolerant architecture of flip-flops for transient pulses and signal delays  
A method and apparatus for a structure of a flip-flop that is tolerant to the noise pulses occurring due to the presence of crosstalk faults by sampling the input data multiple times before and...
7590910 Tap and linking module for scan access of multiple cores with IEEE 1149.1 test access ports  
An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and...
7590909 In-circuit testing system and method  
An in-circuit testing system comprises an integrated circuit having a tri-state control pin used for inducing a tri-state mode in the integrated circuit during a scan test of the integrated circuit...
7587646 Test pattern generation in residue networks  
Generating a near-minimal test pattern set for overlapping residue circuit trees in a residue network includes resolving a residue function of residue circuits through the network and making note...
7587644 Scan testing using response pattern as stimulus pattern after reset  
Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one circuit, such as circuit 1 , as the scan...
7577887 JTAG interface device of mobile terminal and method thereof  
A JTAG interface device capable of effectively debugging a mobile terminal by interfacing the mobile terminal with a JTAG emulator without an additional interface unit by allocating test pins of...
7574644 Functional pattern logic diagnostic method  
A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on functional failure by determining the...
7574641 Probeless testing of pad buffers on wafer  
The peripheral circuitry ( 350, 360 , ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.
7571402 Scan chain modification for reduced leakage  
A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is...
7571365 Wafer scale testing using a 2 signal JTAG interface  
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2)...
7568142 Boundary scan path method and system with functional and non-functional scan cell memories  
An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A...
7568141 Method and apparatus for testing embedded cores  
The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the...
7560966 Method of testing connectivity using dual operational mode CML latch  
A method of testing connectivity through a plurality of dual purpose current mode logic (“CML”) latch circuits connected in a series is provided. Each of the CML latch circuits are operable to...
7555689 Generating responses to patterns stimulating an electronic circuit with timing exception paths  
Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit design having timing exception paths by more accurately determining the unknown values that...
7555687 Sequential scan technique for testing integrated circuits with reduced power, time and/or cost  
Each portion of an integrated circuit is tested using Automatic test pattern generation (ATPG) technique to detect intra-portion faults. Inter-portion faults are detected by first forming a scan...
7552372 Semiconductor device and test method thereof  
An LSI has bidirectional buffers connected to a boundary scan circuit. The boundary scan circuit 12 has asynchronous setting circuits for setting each bidirectional buffer to input mode or output...
7552360 Debug and test system with format select register circuitry  
A system and method for sharing a communications link between multiple protocols is described that comprises a system comprising a communications interface configured to exchange information with...
7546503 Selecting between tap/scan with instructions and lock out signal  
A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port...
7546498 Programmable logic devices with custom identification systems and methods  
Systems and methods are disclosed herein to provide techniques for providing programmable identification codes (IDCODE) for PLDs. For example, in accordance with an embodiment of the present...
7543208 JTAG to system bus interface for accessing embedded analysis instruments  
Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, mechanisms, and means for providing a JTAG to system bus interface for accessing embedded analysis...
7536616 JTAG testing arrangement  
JTAG test equipment arranged to establish an asynchronous data transmission connection with a JTAG-compatible device under test for the transmission of test data between test access ports (TAP) in...
7533315 Integrated circuit with scan-based debugging and debugging method thereof  
An integrated circuit comprises a test interface, an embedded in-circuit emulator, a circuit-under-debugging, and a memory. The embedded in-circuit emulator is used for software debugging via the...
7529995 Second state machine active in first state machine SHIFT-DR state  
Serial scanning circuitry is connectable to test access port controller for transferring serial data to and from functional circuitry. The test access port controller includes a first state machine...
7529994 Analysis apparatus and analysis method  
There is provided an analysis apparatus 30 for analyzing test results of testing, by using a test apparatus, a plurality of devices under test having the same configuration. The analysis...
7525305 Core wrappers with input and output linking circuitry  
A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores...
7523372 Phase shifter with reduced linear dependency  
A method is disclosed for the automated synthesis of phase shifters. Phase shifters comprise circuits used to remove effects of structural dependencies featured by pseudo-random test pattern...
7519889 System and method to reduce LBIST manufacturing test time of integrated circuits  
A method to reduce logic built in self test manufacturing test time of integrated circuits, comprising: loading a plurality of test seeds in bulk into a locally accessible on-chip memory array...
7519883 Method of configuring a system and system therefor  
A first scan data is received at a first scan chain and a representation of the first scan data is subsequently provided from the first scan chain to a second scan chain to test the second scan...
7519880 Burn-in using system-level test hardware  
A burn-in test system. A burn-in test system includes a device under test (DUT), a temperature controller coupled to the DUT, and a test controller. During testing, the test controller: (a) sets a...
7516378 Internal core connected to bond pads by distributor and collector  
Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and...
7516376 Test pattern generator, test circuit tester, test pattern generating method, test circuit testing method, and computer product  
A test circuit tester includes a scan-chain input-output information generator that generates information for an input and an output of the scan chain that is scan-chain input-output information,...
7512856 Register circuit, scanning register circuit utilizing register circuits and scanning method thereof  
The present invention discloses a register circuit. The register circuit includes a latch circuit for latching an input data to generate an output data; an input signal selecting circuit, coupled...
7506233 Interface circuit and method of testing or debugging semiconductor device using it  
An interface circuit includes a selection circuit receiving first and second signals, generating a time division serial signal by selecting one of the first and second signals in response to the...
Matches 1 - 50 out of 552 1 2 3 4 5 6 7 8 9 10 11 12 >