Match Document Document Title
9043664 I/O linking, TAP selection and multiplexer remove select control circuitry  
Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it...
9037932 Position independent testing of circuits  
Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and...
9026872 Flexible sized die for use in multi-die integrated circuit  
An integrated circuit (IC) structure can include a first die and a second die. The second die can include a first base unit and a second base unit. Each of the first base unit and the second base...
9021323 Test techniques and circuitry  
Circuits and a method for testing an integrated circuit (IC) are disclosed. A disclosed circuit block includes a selector circuit that is coupled to receive an enable signal and two clock signals....
9015544 Accelerating scan test by re-using response data as stimulus data abstract  
Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one circuit, such as circuit 1, as the scan...
9015543 Diagnosis-aware scan chain stitching  
Aspects of the invention relate to techniques for determining scan chains that could be diagnosed with high resolution. A circuit design and the information of scan cells for the circuit design...
9009552 Scan-based reset  
Scan-based reset utilizes already existing design-for-test scan chains to reset control and logic circuitry upon reset conditions, such as power-up reset. Such utilization eliminates the need for...
9009554 IC class T0-T2 taps with and without topology selection logic  
Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal...
9003250 Compressor inputs from scan register output and input through flip-flop  
The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan...
9003249 IC test circuitry with tri-state buffer, comparator, and scan cell  
A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the...
8996938 On-chip service processor  
An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component...
8996941 Test data volume reduction based on test cube properties  
Background scan cells are selected from scan cells in a circuit based on specified bit distribution information for a plurality of test cubes generated for testing the circuit. A main portion and...
8996940 Semiconductor integrated circuit and power-supply voltage adaptive control system  
A semiconductor integrated circuit has: N input terminals; N output terminals; a plurality of flip-flops including N flip-flops and R redundant flip-flops; a selector section configured to select...
8990650 TCA with scan paths, decompressor, compressor, and output shift register  
The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access...
8990649 Access port selector for access port and compliant access port  
The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports...
8990623 Avoiding BIST and MBIST intrusion logic in critical timing paths  
Methods, systems, and apparatuses are presented that remove BIST intrusion logic from critical timing paths of a microcircuit design without significant impact on testing. In one embodiment, BIST...
8990648 Optimized synchronous scan flip flop circuit  
According to at least one exemplary embodiment, a synchronous active high reset scan flip flop is provided. The synchronous active high reset scan flip flop may include a data input, a serial...
8984359 Base, IC, and coupling interposer with boundary scan register  
The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1...
8984358 IC TAP with address, state monitor, and state decode circuitry  
The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for...
8984319 Adapter power up circuitry forcing tap states and decoupling tap  
A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during...
8984357 Wrapper selector data register having control outputs and SELECTAM input  
A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and...
8977916 Using data watchpoints to detect unitialized memory reads  
A method of detecting uninitialized memory reads is shown where either all or a subset of a random access memory system is initialized to a know value. One or more watch points are implemented...
8977920 DDR circuitry data and control buses connected to test circuitry  
A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is...
8977918 IC with connections between linking module and test access ports  
An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and...
8977917 Highly secure and extensive scan testing of integrated circuits  
In one embodiment, an integrated circuit chip has an input/output (I/O) interface and programmable fabric. The I/O interface restricts access to scan testing of the chip by requiring (1) a...
8972807 Integrated circuits capable of generating test mode control signals for scan tests  
Various embodiments of methods and integrated circuits capable of generating a test mode control signal for a scan test through a scan chain (such as in an integrated circuit) are provided. The...
8972810 I/O circuitry free of test clock coupled with destination/source circuitry  
The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK...
8959396 Commandable data register control router connected to TCK and TDI  
The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to...
8947070 Apparatus and method for testing driver writeability strength on an integrated circuit  
An apparatus and method for testing driver write-ability strength on an integrated circuit includes one or more drive detection units each including a number of drivers. At least some of the...
8941400 Parallel scan paths with three bond pads, distributors and collectors  
An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus...
8943376 Position independent testing of circuits  
Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and...
8938651 Blocking the effects of scan chain testing upon a change in scan chain topology  
A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection...
8935585 Tap controller having TMS, TCK, enable inputs and control outputs  
An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module....
8935582 Generating test sets for diagnosing scan chain failures  
Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example,...
8924802 IC TAP with dual port router and additional capture input  
This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to...
8924795 Distributed debug system  
A distributed debug system including processing elements connected to perform a plurality of processing functions on a received data unit, a debug trap unit, a debug trace dump logic unit, and a...
8924801 At-speed scan testing of interface functional logic of an embedded memory or other circuit core  
An integrated circuit comprises scan test circuitry and at least one circuit core coupled to the scan test circuitry. The scan test circuitry comprises input and output scan chains coupled to...
8924804 Synchronizer and buffers delaying strobe to individual parallel scan paths  
Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of...
8924803 Boundary scan test interface circuit  
The invention provides a boundary scan test interface circuit. The boundary scan test interface circuit includes N test input pads, a test interfacing module and M test output pads, wherein N and...
8918688 Gating WSP capture and TAP ShiftDR with TAP IR enable  
In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is...
8914693 Apparatus for JTAG-driven remote scanning  
A scan circuit (JTAG 1149 extension) for a microprocessor utilizes transport logic and scan chains which operate at a faster clock speed than the external JTAG clock. The transport logic converts...
8914692 DRAM test architecture for wide I/O DRAM based 2.5D/3D system chips  
A 2.5D or 3D test architecture includes a logic die, and a memory die. In the 2.5D architecture, the logic die and memory die are mounted on an interposer. In the 3D architecture, the memory die...
8904253 Method and apparatus for testing I/O boundary scan chain for SoC's having I/O's powered off by default  
Methods and apparatus for testing Input/Output (I/O) boundary scan chains for Systems on a Chip (SoCs) having I/Os that are powered off by default. Some methods and apparatus include...
8904254 Combo dynamic flop with scan  
A combo dynamic flop with scan flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a dynamic latch circuit and a static...
8898528 DDR JTAG interface setting flip-flops in high state at power-up  
A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by...
8892973 Debugging control system using inside core event as trigger condition and method of the same  
A debugging control system using inside-core events as trigger conditions and a method of the same are revealed. The method includes following steps. First set up at least one trigger condition...
8887016 IC and a method of testing a transceiver of the IC  
An integrated circuit (IC) is provided. The IC includes a transceiver, a boundary scan chain and a plurality of routable pathways. The transceiver includes an interconnection coupling circuit...
8887017 Processor switchable between test and debug modes  
A processor includes a TCU TAP for access of a TCU for running functional tests and a DAP TAP for access of a debugger. A TAP selection module selects reversibly TAP access by default through the...
8880967 Semiconductor test system and method  
A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the...
8880968 Interposer having functional leads, TAP, trigger unit, and monitor circuitry  
The disclosure describes a novel method and apparatus for improving interposers to include embedded monitoring instruments for real time monitoring digital signals, analog signals, voltage signals...