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7617431 |
Method and apparatus for analyzing delay defect
The apparatus for analyzing a delay defect of the present invention obtains the RC of the maximal incidence among region codes (RCs) to which check circuits detecting errors caused with gradual...
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7617429 |
Automatable scan partitioning for low power using external control
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan...
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7617425 |
Method for at-speed testing of memory interface using scan
A method and a circuit of testing of a memory interface associated with an embedded memory in a semiconductor circuit involves writing to two memory locations in succession; reading the two memory...
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7613972 |
Semiconductor integrated circuit, and designing method and testing method thereof
A semiconductor integrated circuit comprises a combinational circuit section having a combinational circuit, a scan path circuit for inputting and outputting a value from and to the combinational...
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7613971 |
Semiconductor integrated circuit with delay test circuit, and method for testing semiconductor integrated circuit
A semiconductor integrated circuit includes an input side flip-flop; a combinational circuit having an input connected with the input side flip-flop; an output side flip-flop connected with an...
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7613969 |
Method and system for clock skew independent scan register chains
A method and system for clock skew independent scan chains. In one embodiment, a method comprises connecting a plurality of mux-D scan registers in a chain configuration, wherein a first mux-D scan...
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7613967 |
Inversion of scan clock for scan cells
A device includes a scan circuit including a scan chain. The scan chain includes a first plurality of scan cells that receive a first scan clock signal in a first clock domain. A second plurality...
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7610534 |
Determining a length of the instruction register of an unidentified device on a scan chain
Methods and systems are provided for determining a total length of instruction registers. A data shift of a scan chain determines whether each device in the scan chain is an identified device. An...
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7610533 |
Semiconductor integrated circuit and method for testing the same
In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply...
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7610531 |
Modifying a test pattern to control power supply noise
Mechanisms for modifying a test pattern to control power supply noise are provided. A portion of a sequence of states in a test sequence of a test pattern waveform is modified so as to achieve a...
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7607059 |
Systems and methods for improved scan testing fault coverage
Systems and methods for improved fault coverage of logic built-in-self-tests (LBISTs) in integrated circuits (ICs) which ensure testing of specific logic by forcing specific values into scan...
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7607056 |
Semiconductor test apparatus for simultaneously testing plurality of semiconductor devices
Disclosed herein is a semiconductor test apparatus for simultaneously testing a plurality of semiconductor devices. The semiconductor test apparatus includes a plurality of pattern generation...
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7600167 |
Flip-flop, shift register, and scan test circuit
A flip-flop has a first latch and a second latch. The first latch has a first feedback circuit and a first selecting circuit which selects one of a first data input signal and an output signal of...
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7600166 |
Method and system for providing trusted access to a JTAG scan interface in a microprocessor
A method for securing a scan chain architecture by performing an authentication operation through a trusted software layer to authorize use of a protected scan chain.
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7596737 |
System and method for testing state retention circuits
This invention discloses a system and method for testing a plurality of state retention circuits in an integrated circuit (IC) chip, that comprises a built-in test circuit configured to invoke a...
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7596734 |
On-Chip AC self-test controller
A system for performing AC self-test on an integrated circuit that includes a system clock for normal operation is provided. The system includes the system clock, self-test circuitry, a first and...
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7596733 |
Dynamically reconfigurable shared scan-in test architecture
A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per...
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7596732 |
Digital storage element architecture comprising dual scan clocks and gated scan output
A digital storage element (e.g., a flip-flop or a latch) includes a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave...
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7594150 |
Fault-tolerant architecture of flip-flops for transient pulses and signal delays
A method and apparatus for a structure of a flip-flop that is tolerant to the noise pulses occurring due to the presence of crosstalk faults by sampling the input data multiple times before and...
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7594149 |
In-situ monitor of process and device parameters in integrated circuits
In accordance with the invention, a testing circuit formed on the integrated circuit is presented. A testing circuit according to the present invention is coupled to a scan path circuit and...
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7590908 |
Semiconductor integrated circuit and method for testing the same
In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply...
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7590907 |
Method and apparatus for soft-error immune and self-correcting latches
A scanned value is stored by loading the value into at least three latch stages, generating an output value based on a majority of the latch stage outputs, and feeding the output value back to the...
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7590906 |
Scan flip-flop circuit and semiconductor integrated circuit device
Disclosed is a scan flip-flop that includes a latch section, a hold section, a first output node and a second output node. The latch section holds data. The hold section captures an inner state,...
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7590905 |
Method and apparatus for pipelined scan compression
A pipelined scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation...
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7587643 |
System and method of integrated circuit testing
An integrated circuit may include a packet decoder to receive serial data and to decode JTAG signals from the packets received. A JTAG processor may test the electrical circuitry dependent on the...
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7584393 |
Scan test circuit and method of arranging the same
Replaced cell CELL 1 is composed of clock buffer circuit CB 1 and flip-flop circuit FF 1 that latches data at a falling-down time of a clock signal. Clock buffer circuits CB 1 a -CB 1 d are...
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7584392 |
Test compaction using linear-matrix driven scan chains
A scan technique using linear matrix to drive scan chains is used, along with an ATPG, to constraint scan test vectors to be generated through the linear matrix. The linear matrix scan technique...
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7581150 |
Methods and computer program products for debugging clock-related scan testing failures of integrated circuits
The present invention is directed to a method for debugging scan testing failures of integrated circuits. The method includes identifying good and bad scan paths among a set of scan paths. A scan...
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7581149 |
Scan chain extracting method, test apparatus, circuit device, and scan chain extracting program
A scan-chain extracting method of the present invention includes a defining step of defining control-circuit scan chains provided in a test control circuit; an initial-value setting step of setting...
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7577887 |
JTAG interface device of mobile terminal and method thereof
A JTAG interface device capable of effectively debugging a mobile terminal by interfacing the mobile terminal with a JTAG emulator without an additional interface unit by allocating test pins of...
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7574644 |
Functional pattern logic diagnostic method
A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on functional failure by determining the...
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7574642 |
Multiple uses for BIST test latches
A method is provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in...
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7574640 |
Compacting circuit responses
A compactor has a reduced number of outputs and the ability to handle a higher number of errors and unknown logic values. The procedure for designing the matrix and the resulting compactor involves...
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7574638 |
Semiconductor device tested using minimum pins and methods of testing the same
The present invention provides semiconductor devices capable of being tested using one test pin and using an input/output pin without any test pins, and methods of testing the same. One...
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7571402 |
Scan chain modification for reduced leakage
A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is...
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7571364 |
Selectable JTAG or trace access with data store and output
An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and TDI input from a single data pin....
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7570076 |
Segmented programmable capacitor array for improved density and reduced leakage
A capacitor circuit and method to reduce layout area, leakage current, and to improve yield is disclosed. The circuit includes an output terminal ( 100 ), a plurality of circuit elements ( 322,...
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7568141 |
Method and apparatus for testing embedded cores
The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the...
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7568140 |
Integrated circuit having configurable cells and a secured test mode
An electronic circuit includes a plurality of configurable cells configured by a control circuit such as a test access controller when it receives a mode command signal: either in a functional...
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7568139 |
Process for identifying the location of a break in a scan chain in real time
A process for identifying the location of a break in a scan chain in real time as fail data is collected from a tester. Processing a test pattern before applying it on a tester provides a signature...
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7568138 |
Method to prevent firmware defects from disturbing logic clocks to improve system reliability
A computer implemented method and data processing system are provided for preventing firmware defects from disrupting logic clocks. In response to a firmware interface requesting a scan operation...
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7565591 |
Testing of circuits with multiple clock domains
Consistent with an example embodiment, the amount of time required for testing circuits that contain a plurality of different clock domains is reduced. According to the embodiment, during selection...
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7565588 |
Semiconductor device and data storage apparatus
A semiconductor device and a data storage apparatus are provided. A semiconductor device includes: a cell array configured to have cells for data storage arranged in an array; at least one buffer...
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7562276 |
Apparatus and method for testing and debugging an integrated circuit
An integrated circuit (IC) comprises an embedded processor. An embedded in-circuit emulator (ICE) emulates at least one function of the embedded processor, performs at least one of testing and...
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7562275 |
Tri-level test mode terminal in limited terminal environment
A technique for increasing functionality of terminals of an integrated circuit without increasing the number of terminals of the integrated circuit utilizes at least one tri-level terminal and...
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7562274 |
User data driven test control software application the requires no software maintenance
Methods and apparatus for performing a data driven test on a circuit including at least one built-in-self-test compatible device. In one embodiment, the method includes describing the device using...
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7562273 |
Register file cell with soft error detection and circuits and methods using the cell
Techniques are provided for a register file cell that includes a primary storage portion configured to store a first value, and a secondary storage portion that is coupled to the primary storage...
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7562272 |
Apparatus and method for using eFuses to store PLL configuration data
An apparatus and method for using electrical fuses (eFuses) to store phase-locked loop (PLL) configuration data are provided. With the apparatus and method, a portion of the eFuses present in the...
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7560966 |
Method of testing connectivity using dual operational mode CML latch
A method of testing connectivity through a plurality of dual purpose current mode logic (“CML”) latch circuits connected in a series is provided. Each of the CML latch circuits are operable to...
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7558998 |
Semiconductor apparatus and clock generation unit
A semiconductor apparatus generates a clock signal used for scan test on an internal circuit of the semiconductor apparatus. The semiconductor apparatus includes a scan chain for performing input...
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