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7392447 Method of using scan chains and boundary scan for power saving  
The invention provides a method and circuitry to save power in a synchronous logic ASIC with low overhead. The scan chain(s) and boundary scan mechanism of the synchronous logic ASIC are used and...
7392448 Method and apparatus for determining stuck-at fault locations in cell chains using scan chains  
Methods and apparatus are provided for testing digital circuits. In one implementation, a scan chain test structure is provided that includes a cell chain, a first scan chain, and a second scan...
7389455 Register file initialization to prevent unknown outputs during test  
A system and method for initializing a register file during a test period for an integrated circuit, wherein the register file has one or more input ports. A counter, when enabled, is initialized...
7389454 Error detection in user input device using general purpose input-output  
A method and apparatus are disclosed for using a general purpose input-output (GPIO) interface to test a user input device such as a wireless keyboard or mouse. Operation of key-scan logic can be...
7386774 Memory unit with controller managing memory access through JTAG and CPU interfaces  
A memory unit includes a memory organized into protected and non-protected areas. A controller manages access to the memory so that the protected area can be written to through a JTAG or CPU...
7383480 Scanning latches using selecting array  
A method and system for scanning data from a specific latch in a matrix array of latches. The matrix array is made up of vertical selector lines and horizontal data lines. Each latch is coupled at...
7383478 Wireless dynamic boundary-scan topologies for field  
A programmable logic device (PLD) with a JTAG port, such as an FPGA, is provided with a wireless JTAG adapter to enable wireless communications. Multiple PLDs connected with wireless-to-JTAG...
7383481 Method and apparatus for testing a functional circuit at speed  
An integrated circuit including functional circuitry; test circuitry connected to the functional circuitry, wherein the test circuitry is arranged to control the testing of the functional...
7380184 Sequential scan technique providing enhanced fault coverage in an integrated circuit  
According to an aspect of the present invention, multiple scan enable signals (controlling corresponding scan chains) are used in an integrated circuit, and the scan chains are placed in evaluation...
7380187 Boundary scan tester for logic devices  
A boundary scan tester is provided for testing logic devices. The boundary scan tester includes a boundary scan register, a data decompressor, a data compressor, and a derived boundary scan...
7380185 Reduced pin count scan chain implementation  
The synchronous logic device with reduced pin count scan chain includes: more than two flip/flops coupled to form a shift register for receiving a scan data input signal; a combinational logic...
7380183 Semiconductor circuit apparatus and scan test method for semiconductor circuit  
A semiconductor circuit apparatus, on which a scan test can be conducted, has a plurality of circuit sections. The semiconductor circuit apparatus includes a scan chain having a plurality of...
7375549 Reconfiguration of programmable logic devices  
Improved reconfiguration techniques are provided for programmable logic devices (PLDs). For example, in accordance with an embodiment of the present invention, a programmable logic device includes...
7376875 Method of improving logical built-in self test (LBIST) AC fault isolations  
A system, apparatus and method of isolating a plurality of limiting logical cones in a chip during a logical built-in self test (LBIST) are provided. An LBIST is performed on the chip in order to...
7373567 System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA  
A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide...
7373569 Pulsed flop with scan circuitry  
In one embodiment, a storage circuit comprises a first passgate having an input coupled to receive a signal representing a data input to the storage circuit and further having an output connected...
7373573 Apparatus and method for using a single bank of eFuses to successively store testing data from multiple stages of testing  
An apparatus and method for using a single bank of electric fuses (eFuses) to successively store test data derived from multiple stages of testing are provided. To encode and store array redundancy...
7373568 Scan insertion  
An integrated circuit comprises n storage elements, arranged to form a scan chain, that define m clock domains, wherein m≧2 and n≧m. A clock driver is adapted to provide m domain clock signals...
7373570 LSI device having scan separators provided in number reduced from signal lines of combinatorial circuits  
A scan separator in a large scale integration device is made more extensive to suppress an increase in the circuit scale of the entire device. In one embodiment, a scan separator is provided for...
7373571 Achieving desired synchronization at sequential elements while testing integrated circuits using sequential scan techniques  
A programmable delay circuit is provided in either data input path or a clock input path of a sequential element contained in a scan chain of an integrated circuit. The scan chain is used to test...
7373574 Semiconductor testing apparatus and method of testing semiconductor  
A semiconductor testing apparatus, includes a test signal generating unit that generates a test signal corresponding to a test pattern to output the generated test signal to a device under test...
7370255 Circuit testing with ring-connected test instrument modules  
Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master...
7370254 Compressing test responses using a compactor  
The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can...
7363564 Method and apparatus for securing communications ports in an electronic device  
An apparatus comprises at least one port for coupling signals to the apparatus, a mode selector for setting the apparatus to a normal mode or a debug mode, and a port control for controlling access...
7363559 Detection of tap register characteristics  
According to some embodiments, first data including a token is shifted into an IEEE 1149.1-compliant shift register and second data is received, the second data being shifted out from the IEEE...
7360133 Method for creating a JTAG tap controller in a slice for use during custom instance creation to avoid the need of a boundary scan synthesis tool  
A method and system is provided for creating a tap controller in a slice for use during custom instance creation to avoid the need of a boundary scan synthesis tool. Aspects of the present...
7359820 In-cycle system test adaptation  
Disclosed are a method, information processing system and computer readable medium for performing a system test on a program. The method comprises creating a test plan associated with a system...
7355430 Parallel scan distributors and collectors and process of testing integrated circuits  
An integrated circuit ( 70 ) having parallel scan paths ( 824 - 842, 924 - 942 ) includes a pair or pairs of scan distributor ( 800,900 ) and scan collector ( 844,944 ) circuits. The scan paths...
7356745 IC with parallel scan paths and compare circuitry  
A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control...
7353441 Flip flop circuit and apparatus using a flip flop circuit  
A flip flop circuit includes a first latch circuit which latches an input data at a leading edge of a clock signal, a second latch circuit which latches the input data at a trailing edge of the...
7353440 Multicore processor test method  
In processors having multiple cores, such as CMPs, an independent MISR test pattern compression circuit is provided for each logic block, which makes it possible to perform LSI tests more...
7350124 Method and apparatus for accelerating through-the pins LBIST simulation  
The present invention provides a method, an apparatus, and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set...
7346819 Through-core self-test with multiple loopbacks  
An integrated circuit device having a test sequence generator, first and second transceivers and a test sequence analyzer. The test sequence generator generates a test data sequence in response to...
7346820 Testing of data retention latches in circuit devices  
A circuit device having data retention latches utilizes a test interface and system test controller to control one or more components of the circuit device to ensure proper conditions for testing...
7343537 IC with protocol selection memory coupled to serial scan path  
A digital bus monitor used to observe data on a bus ( 14, 16, 18 ) connecting multiple integrated circuits ( 10, 12 ) comprises a memory buffer ( 30 ), bypass register ( 34 ), test port ( 38 ) and...
7343536 Scan based automatic test pattern generation (ATPG) test circuit, test method using the test circuit, and scan chain reordering method  
A scan based Automatic Test Pattern Generation (ATPG) test circuit, a test method using the test method, and a scan chain reordering method are disclosed. The test circuit tests for scan chains...
7340658 Technique for combining scan test and memory built-in self test  
Semiconductor devices including logic circuitry and embedded memories may be tested using one or more flip-flops in a scan chain that are connected to a control input of an MBIST logic, thereby...
7340659 Method of testing multiple modules on an integrated circuit  
An integrated circuit ( 20 ) comprises a plurality of processing modules ( 3, 5, 7 ) which interact during the normal operation of the integrated circuit. Switches ( 13, 15 ) are provided on the...
7337100 Physical resynthesis of a logic design  
A multiple-pass synthesis technique improves the performance of a design. In a specific embodiment, synthesis is performed in two or more passes. In a first pass, a first synthesis is performed,...
7332929 Wide-scan on-chip logic analyzer with global trigger and interleaved SRAM capture buffers  
A system chip has many local blocks including processor cores, caches, and memory controllers. Each local block has a local sample-select mux that is controlled by a local selection control...
7334173 Method and system for protecting processors from unauthorized debug access  
A method for securing a scan test architecture by performing an authentication operation to authorize use of a protected scan chain.
7332928 Use of a third state applied to a digital input terminal of a circuit to initiate non-standard operational modes of the circuit  
A circuit module having one of more digital input terminals that are capable of receiving a third input state to initiate non-standard operational modes such as might be desired during programming...
7334172 Transition fault detection register with extended shift mode  
An apparatus includes a register of an integrated circuit for shifting a scan test pattern in response to a scan enable signal. The register includes: a shift input for receiving the scan test...
7330994 Clock control of a multiple clock domain data processor  
A processor clock control device operable to control a plurality of clock signals output to a processor, said processor comprising a plurality of domains each clocked by a respective one of said...
7328385 Method and apparatus for measuring digital timing paths by setting a scan mode of sequential storage elements  
A method and apparatus are provided for performing on-board, in-circuit, and/or wafer level scan-based testing of integrated circuits. With the apparatus and method, one or more sequential storage...
7328387 Addressable tap domain selection circuit with selectable ⅗ pin interface  
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the...
7328386 Methods for using checksums in X-tolerant test response compaction in scan-based testing of integrated circuits  
The invention relates to a method for using checksums in X-tolerant test response compaction in scan-based testing of integrated circuits. Flip-flops of a chip are treated as points of a discrete...
7324932 Virtual test environment  
A method of and an apparatus for designing a test environment providing reliable test signal integrity, and of evaluating performance of the test environment and an electronic device during testing...
7321999 Methods and apparatus for programming and operating automated test equipment  
In one embodiment, an electronic device is tested using automated test equipment (ATE) by 1) storing different vectors of scan load data in memory of the ATE; 2) storing a scan unload subroutine in...
7320097 Serial to parallel conversion circuit having a shift clock frequency lower than a data transfer frequency  
A serial to parallel conversion circuit is provided. The circuit includes a shift register including flip-flops latch circuits, and control circuits. The flip-flops are connected in cascade, with a...
Matches 201 - 250 out of 1005 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >