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7454676 Method for testing semiconductor chips using register sets  
A method for testing semiconductor chips having a test logic unit includes: providing a chip having n different register sets, each of which has m different registers that are subdivided into m...
7454677 Two boundary scan cell switches controlling input to output buffer  
A process initializes the state of an output memory circuit of a scan cell located at the boundary of a logic circuit within an integrated circuit. Data is scanned into an input memory circuit of...
7454675 Testing of a programmable device  
A method of testing a programmable device begins by programming at least a portion of the programmable device in accordance with at least a portion of an application to produce a programmed...
7451373 Circuit for compression and storage of circuit diagnosis data  
A compactor includes test data inputs that are connectable to circuit outputs of an electrical circuit, test comparison inputs, and test data outputs. The compactor further includes a number of H...
7447960 Method of efficiently loading scan and non-scan memory elements  
The present invention provides a method and apparatus for efficiently loading values into scan and non-scan memory elements. First, the network used to distribute control signals to the memory...
7447961 Inversion of scan clock for scan cells  
In one embodiment, an apparatus comprises a scan circuit including at least a first and a second clock domain and a scan chain having a first plurality of scan cells positioned in the first clock...
7447962 JTAG interface using existing I/O bus  
A plurality of input circuits and a plurality of output circuits are connected to form a Boundary Scan Path Chain (BSPC). Part or all of the existing I/O bus is used as a test bus. When a test...
7444556 System and method of interleaving transmitted data  
A method ( 500 ) is provided for operating an interleaver circuit 120 having N shift lines ( 220 1 - 220 N ). Each shift line has a line input node, a line output node, and one or more bit...
7444568 Method and apparatus for testing a data processing system  
A method for testing at least one logic block of a processor includes, during execution of a user application by the processor, the processor generating a stop and test indicator. In response to...
7444570 Apparatus and method for controlling frequency of an I/O clock for an integrated circuit during test  
A test system including a device under test (DUT) and a tester, where the DUT includes I/O interface logic and a clock circuit. The clock circuit includes a core clock circuit, a pad clock circuit,...
7444567 Method and apparatus for unifying self-test with scan-test during prototype debug and production test  
A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test...
7441171 Efficient scan chain insertion using broadcast scan for reduced bit collisions  
Disclosed is a method of inserting scan elements onto scan chains of broadcast scan structures to minimize the number of collisions in a plurality of logic cones. Each logic cone is selected and...
7441164 Memory bypass with support for path delay test  
A method and apparatus are described for testing at least one critical data path in a design of a digital integrated circuit chip during a simulation of the design. A dedicated memory-bypass-enable...
7441169 Semiconductor integrated circuit with test circuit  
A semiconductor integrated circuit has a scan path that includes, between the output of the first logic section and the input of the functional block, a parallel path and a serial shift path for...
7436211 Transparent latch circuit  
The present invention provides a transparent latch circuit capable of performing a scan test in general scan design (GSD). In the transparent latch circuit a test signal is at a Low level during...
7437636 Method and apparatus for at-speed testing of digital circuits  
Exemplary schemes for multi-frequency at-speed logic Built-In Self Test (BIST) are provided. For example, certain schemes allow at-speed testing of very high frequency integrated circuits...
7437645 Test circuit for semiconductor device  
A semiconductor test circuit includes an input terminal, a controller, a setting circuit, a command generator, a transmission path switching circuit and a comparator. The input terminal receives a...
7437634 Test scan cells  
A sequential scan cell includes an input port for functional data and an input for scan test data. The input for scan test data is an input to a master scan flip-flop coupled to a slave scan...
7437637 Apparatus and method for programmable fuse repair to support dynamic relocate and improved cache testing  
An apparatus and method for allowing for dynamic wordline repair in a clock running system in addition to allowing for programmable fuse support of combined Array Built-In Self-Test (ABIST) and...
7437635 Testing hard-wired IP interface signals using a soft scan chain  
A set of boundary scan registers are implemented by reconfiguring the functional blocks of a reconfigurable device. This “soft-wired” set of boundary scan registers can be used to test the...
7437638 Boundary-Scan methods and apparatus  
Disclosed herein are various methods and apparatus related to Boundary-Scan testing, including a method for generating Boundary-Scan test vectors. The method assigns different binary signatures to...
7434127 eFuse programming data alignment verification apparatus and method  
An eFuse data alignment verification apparatus and method are provided. Alignment latches are provided in a series of latch units of a write scan chain and a logic unit is coupled to the alignment...
7430698 Method and system for an on-chip AC self-test controller  
A method and system for performing AC self-test on an integrated circuit that includes a system clock for use during normal operation are provided. The method includes applying a long data capture...
7430697 Method of testing circuit blocks of a programmable logic device  
A method of testing circuits in a programmable logic device is described. According to one embodiment of the invention, a method comprises steps of configuring a configurable logic block of the...
7428676 Boundary scan device  
A boundary-scan device in which a plurality of signal paths are connected to the macro, each having a data signal input end and a data signal output end for signal transmission during normal mode...
7428674 Monitoring the state vector of a test access port  
Monitoring of the state vector of a test access port (TAP) permits isolation of the root cause of improper transitions of the state vector due to various factors, including electrical noise. The...
7428675 Testing using independently controllable voltage islands  
A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of...
7426670 Connecting multiple test access port controllers on a single test access port  
Multiple test access port (TAP) controllers on a single chip are accessed, while maintaining the appearance to an outside observer of having only a single test access port controller. By adding a...
7424417 System and method for clock domain grouping using data path relationships  
A method and system are disclosed, in a simulation of a design of a digital integrated circuit chip, to limit a number of scan test clocks and chip ports used for testing the chip. Clock domains...
7423449 Electronic circuit  
An electronic circuit is provided that comprises first and second combinational logic blocks and a latch positioned between the combinational logic blocks; wherein the electronic circuit is adapted...
7424656 Clocking methodology for at-speed testing of scan circuits with synchronous clocks  
A clocking method for at-speed scan testing for delay defects in cross-domain paths of interacting synchronous clock domains in a scan circuit, each path originating from a source memory element in...
7421634 Sequential scan based techniques to test interface between modules designed to operate at different frequencies  
According to an aspect of present invention, modules designed to operate with different frequency in functional (normal) mode are tested using a sequential scan based technique at the respective...
7421384 Semiconductor integrated circuit device and microcomputer development supporting device  
During software development, a multichip module is used which encloses a target chip and a development chip in one package. A CPU of the development chip fetches instructions from a flash memory in...
7421633 Controller receiving combined TMS/TDI and suppyling separate TMS and TDI  
An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than...
7418640 Dynamically reconfigurable shared scan-in test architecture  
A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per...
7418641 Self-resetting, self-correcting latches  
A latch circuit having three latch stages generates a majority output value from the stages, senses when the latch stage outputs are not all equal, and feeds the majority output value back to...
7412638 Method, system, and program product for controlling test data of a logic built-in self-test of an integrated circuit  
A method of controlling test data with a boundary latch module having a plurality of latches to facilitate logic built-in self-testing of an integrated circuit (IC) is provided which includes...
7412636 Scan string segmentation for digital test compression  
One may use a new technique to determine the placement of exclusive-ors in each scan string of a chip may achieve improved test vector compression, and one may combine this technique with methods...
7409611 Wrapper instruction/data register controls from test access or wrapper ports  
In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP,...
7406640 Method and apparatus for testing a ring of non-scan latches with logic built-in self-test  
A method and apparatus for loading a ring of non-scan latches for a logic built-in self-test. A logic built-in self-test value is loaded into a scannable latch from the logic built-in self-test. An...
7406641 Selective control of test-access ports in integrated circuits  
To facilitate testing, some integrated circuits include built-in test circuits, called test-access ports (TAPs). The present inventor recognized that TAPs are sometimes used with automatic testers...
7406639 Scan chain partition for reducing power in shift mode  
A scan chain partition includes a serial input coupled to a scan input signal pin of a module under test. A plurality of scan sub-chains is coupled to the serial input. A scan sub-chain output...
7404125 Compilable memory structure and test methodology for both ASIC and foundry test environments  
A memory structure configured for supporting multiple test methodologies includes a first plurality of multiplexers configured for selectively coupling at least one data input path and at least one...
7404129 TAP IR control with TAP/WSP or WSP DR control  
In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered...
7404126 Scan tests tolerant to indeterminate states when employing signature analysis to analyze test outputs  
Scan tests tolerant to indeterminate states generated in an integrated circuit (IC) when employing signature analysis to analyze test outputs. Bits with indeterminate-state are masked when scanning...
7404127 Circuitry with multiplexed dedicated and shared scan path cells  
An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A...
7401277 Semiconductor integrated circuit and scan test method therefor  
A method for performing scan test on a semiconductor integrated circuit including at least two blocks to be tested. The method includes isolating each of the at least two blocks to be tested...
7401278 Edge-triggered master + LSSD slave binary latch  
A binary latch that operates as an edge-triggered flip-flop and which is LSSD-testable that comprises an edge triggered master. The binary latch comprises an edge triggered master flip-flop ( 2 ),...
7398424 False path detection program  
A false path detection program whereby passing points of signal lines constituting false paths are directly detected, thereby shortening the processing time necessary for the false path detection...
7397274 In-system programming of a non-compliant device using multiple interfaces of a PLD  
In one embodiment of the invention, a programmable logic device such as an FPGA includes a programmable fabric; a JTAG interface operable to receive configuration data for programming the fabric; a...
Matches 151 - 200 out of 1009 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >