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7509548 Method and apparatus for integrated circuit self-description  
An integrated circuit includes a self-description data store that stores a self-description of at least a portion of the integrated circuit device. The self-description includes at least some...
7509550 Fault diagnosis of compressed test responses  
Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, at least one error...
7509549 Dynamic frequency scaling for JTAG communication  
A system comprising a system under test (SUT) having a control logic. The SUT further comprises testing logic coupled to the SUT and adapted to provide to the SUT a clock signal to facilitate...
7506231 Wrapper testing circuits and method thereof for system-on-a-chip  
A wrapper testing circuit of system-on-a-chip for electrical tests of at least a core circuit of an integrated circuit and a wrapper testing method thereof are provided. A controller outputs...
7506230 Transient noise detection scheme and apparatus  
A method, system and apparatus for detecting soft errors in non-dataflow circuits. In a preferred embodiment, input is received at a latch system. The latch system consists of two pairs of latches....
7506233 Interface circuit and method of testing or debugging semiconductor device using it  
An interface circuit includes a selection circuit receiving first and second signals, generating a time division serial signal by selecting one of the first and second signals in response to the...
7502978 Systems and methods for reconfiguring scan chains  
Systems and methods for reconfiguring scan chains are provided. A representative system incorporates a first scan chain of flip-flops operative in either a normal mode or a rotate mode such that,...
7500164 Method for testing an integrated circuit device having elements with asynchronous clocks or dissimilar design methodologies  
A method for testing an integrated circuit device with asynchronous clocks or dissimilar design methodologies is provided. With the method, each clock domain has its own scan paths that do not...
7500147 Test system and method  
A test system includes a terminal host and a to-be-tested circuit board. The terminal host generates a trigger signal. The to-be-tested circuit board includes a system chip, a memory and a...
7500162 Sourcing internal signals to output pins of an integrated circuit through sequential multiplexing  
An integrated circuit with a multiplexer system and a control circuit is described. The multiplexer system has an output terminal connected to an output pin of the integrated circuit and input...
7496816 Isolating the location of defects in scan chains  
A system and method for isolating defects in scan chains by performing diagnostics fault simulation on chosen faults that are consistent with the nature of a scan chain defect, while keeping...
7496820 Method and apparatus for generating test vectors for an integrated circuit under test  
Method, apparatus, and computer readable medium for generating test vectors for an integrated circuit (IC) under test is described. In one example, a test function is specified using at least one...
7496809 Integrated scannable interface for testing memory  
An integrated scannable interface for testing memory. The interface includes a selection device for selecting a signal from at least two input signals responsive to an activation signal, a first...
7493536 IC input memory with dual data and dual control inputs  
An electronic integrated circuit includes a signal path connected between the functional logic and an external input terminal, which signal path includes a memory circuit. The memory circuit is...
7493540 Continuous application and decompression of test patterns to a circuit-under-test  
A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a...
7490231 Method and system for blocking data in scan registers from being shifted out of a device  
Aspects of a method and system for blocking data in scan registers from being shifted out of a device may comprise preventing data intrusion in an integrated circuit by generating a device reset...
7490273 Auto-calibration method for delay circuit  
An auto-calibration method is applied to a delay circuit, which includes a plurality of delay chains. If the number of accumulative errors of a designated delay chain as a current delay path is...
7487571 Control adjustable device configurations to induce parameter variations to control parameter skews  
A method is used for configuring an electronic device to reduce a skew of a parameter. The method includes a step of incorporating a plurality of controllable built-in parameter variation adjusting...
7487417 Digital storage element with enable signal gating  
A digital storage element (e.g., a flip-flop or a latch) comprise a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave...
7487419 Reduced-pin-count-testing architectures for applying test patterns  
Methods, apparatus, and systems for testing integrated circuits using one or more boundary scan cells are disclosed. The methods, apparatus, and systems can be used, for example, to apply at-speed...
7487412 Test buffer design and interface mechanism for differential receiver AC/DC boundary scan test  
A boundary scan test system including a transmitter and a receiver. The system performs DC and AC boundary scan testing of the interconnections between devices. The system addresses fault masking...
7484151 Method and apparatus for testing logic circuit designs  
Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is...
7484149 Negative edge flip-flops for muxscan and edge clock compatible LSSD  
A method of synchronous digital operation and scan based testing of an integrated circuit using a flip-flop. The flip-flop including a master latch having an input and a clock pin; a slave latch...
7484150 Semiconductor integrated circuit design apparatus and semiconductor integrated circuit design method  
A semiconductor integrated circuit design method is a method for designing a semiconductor integrated circuit having a main circuit as well as the spare cell including a scan flip-flop. In the...
7482851 Latch and clock structures for enabling race-reduced mux scan and LSSD co-compatibility  
An edge triggered system is provided having a data and scan input includes a latch device having a clock input and an AND gate, coupled to the latch device, structured and arranged to receive a...
7484148 Interface error monitor system and method  
An interface error monitor system for monitoring data exchanged between a controller and a data converter over an interface includes a multi-stage linear feedback shifter register associated with...
7480844 Method for eliminating hold error in scan chain  
A method for eliminating a hold error from a scan chain configured by connecting a plurality of data holding circuits with wiring. The method includes reordering the data holding circuits using the...
7478298 Method and system for backplane testing using generic boundary-scan units  
A test system for testing a backplane comprising an adapter assembly and a generic boundary-scan test unit. The adapter assembly includes an application-specific mating connector to communicatively...
7478300 Method for testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device  
A method for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device is provided. With the method, each clock domain has its own scan paths that do not...
7478304 Apparatus for accelerating through-the-pins LBIST simulation  
The present invention provides an apparatus and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a...
7478301 Partial good integrated circuit and method of testing same  
An integrated circuit and method of testing and repairing the integrated circuit. The integrated circuit includes: a multiplicity of macro-circuits having the same function; a fuse bank, the state...
7475306 Scan test method, integrated circuit, and scan test circuit  
A scan test method of an integrated circuit including a combinational circuit and flip-flops forming a scan chain is disclosed. The method first sets an initial test value to the flip-flops forming...
7475308 implementing deterministic based broken scan chain diagnostics  
A method, apparatus and computer program product are provided for implementing deterministic based broken scan chain diagnostics. A deterministic test pattern is generated and is loaded into each...
7475300 Test circuit and test method  
A test method sets a write value to a scan flip-flop for setting a value to a memory to be tested. It then performs a series of shift operation in scan paths until setting of a read value is...
7475309 Parallel test mode for multi-core processors  
An embodiment of the present invention is a technique to provide a parallel test mode for multi-core processors. A test access port (TAP) in a first processor core generates a first test data...
7475315 Configurable built in self test circuitry for testing memory arrays  
Integrated circuits such as programmable logic device integrated circuits are provided that have memory arrays. The memory arrays can be tested using configurable built in self test circuitry. The...
7469372 Scan sequenced power-on initialization  
A scan sequenced initialization technique supplies a predefined power-on state to a device or module without using explicit reset input to the registers. This technique supplies a predefined...
7467340 TAP, ST, lockout, and IR SO enable output data control  
Two common varieties of test interfaces exist for ICs and/or cores, the IEEE 1149.1 Test Access Port (TAP) interface and internal scan test ports. The TAP serves as a serial communication port for...
7464310 Programmable state machine of an integrated circuit  
A programmable state machine of an application specific integrated circuit (ASIC) is programmed by enabling the scan mode of the integrated circuit. The process of programming the state machine...
7461309 Systems and methods for providing output data in an LBIST system having a limited number of output ports  
Systems and methods for performing logic tests in digital circuits with means for segmentation and output of data through limited I/O ports. In one embodiment, a system includes test circuitry...
7461308 Method for testing semiconductor chips by means of bit masks  
A method for testing semiconductor chips is disclosed. In one embodiment, a chip to be tested which has a test logic, at least one test mode is set, the test modes are executed in the chip and test...
7459926 Scan distributor loading scan paths simultaneous with loading test data  
An integrated circuit ( 70 ) having parallel scan paths ( 824 - 842, 924 - 942 ) includes a pair or pairs of scan distributor ( 800,900 ) and scan collector ( 844,944 ) circuits. The scan paths...
7457998 Scan register and methods of using the same  
An improved scan register and methods of using the same have been disclosed. In one embodiment, the improved scan register includes a master latch having a data input, a data output, and a control...
7457999 Debug port system for control and observation  
Some embodiments provide a device under test comprising a processing core to support execution debug signals, a debug ring to receive and to transmit the execution debug signals from and to the...
7454676 Method for testing semiconductor chips using register sets  
A method for testing semiconductor chips having a test logic unit includes: providing a chip having n different register sets, each of which has m different registers that are subdivided into m...
7454677 Two boundary scan cell switches controlling input to output buffer  
A process initializes the state of an output memory circuit of a scan cell located at the boundary of a logic circuit within an integrated circuit. Data is scanned into an input memory circuit of...
7454675 Testing of a programmable device  
A method of testing a programmable device begins by programming at least a portion of the programmable device in accordance with at least a portion of an application to produce a programmed...
7451373 Circuit for compression and storage of circuit diagnosis data  
A compactor includes test data inputs that are connectable to circuit outputs of an electrical circuit, test comparison inputs, and test data outputs. The compactor further includes a number of H...
7447960 Method of efficiently loading scan and non-scan memory elements  
The present invention provides a method and apparatus for efficiently loading values into scan and non-scan memory elements. First, the network used to distribute control signals to the memory...
7447961 Inversion of scan clock for scan cells  
In one embodiment, an apparatus comprises a scan circuit including at least a first and a second clock domain and a scan chain having a first plurality of scan cells positioned in the first clock...
Matches 101 - 150 out of 1003 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >