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7565588 |
Semiconductor device and data storage apparatus
A semiconductor device and a data storage apparatus are provided. A semiconductor device includes: a cell array configured to have cells for data storage arranged in an array; at least one buffer...
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7562273 |
Register file cell with soft error detection and circuits and methods using the cell
Techniques are provided for a register file cell that includes a primary storage portion configured to store a first value, and a secondary storage portion that is coupled to the primary storage...
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7562275 |
Tri-level test mode terminal in limited terminal environment
A technique for increasing functionality of terminals of an integrated circuit without increasing the number of terminals of the integrated circuit utilizes at least one tri-level terminal and...
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7560966 |
Method of testing connectivity using dual operational mode CML latch
A method of testing connectivity through a plurality of dual purpose current mode logic (“CML”) latch circuits connected in a series is provided. Each of the CML latch circuits are operable to...
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7562274 |
User data driven test control software application the requires no software maintenance
Methods and apparatus for performing a data driven test on a circuit including at least one built-in-self-test compatible device. In one embodiment, the method includes describing the device using...
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7562272 |
Apparatus and method for using eFuses to store PLL configuration data
An apparatus and method for using electrical fuses (eFuses) to store phase-locked loop (PLL) configuration data are provided. With the apparatus and method, a portion of the eFuses present in the...
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7562276 |
Apparatus and method for testing and debugging an integrated circuit
An integrated circuit (IC) comprises an embedded processor. An embedded in-circuit emulator (ICE) emulates at least one function of the embedded processor, performs at least one of testing and...
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7558997 |
Wiring structure and method of semiconductor integrated circuit
To provide wiring structure and method capable of supplying a scan clock signal for each clock domain without requesting a user to add a test circuit. The wiring structure of a semiconductor...
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7558998 |
Semiconductor apparatus and clock generation unit
A semiconductor apparatus generates a clock signal used for scan test on an internal circuit of the semiconductor apparatus. The semiconductor apparatus includes a scan chain for performing input...
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7558996 |
Systems and methods for identifying errors in LBIST testing
Systems and methods for controlling the execution of LBIST test cycles to allow identification of errors in bit patterns produced by the functional logic of a device under test. In one embodiment,...
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7555422 |
Preserving emulation capability in a multi-core system-on-chip device
A system comprises a multi-core silicon-on-chip (SOC) device. The SOC device includes a core module, a test data shift path, a core power control module, and an emulation control module. The core...
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7555687 |
Sequential scan technique for testing integrated circuits with reduced power, time and/or cost
Each portion of an integrated circuit is tested using Automatic test pattern generation (ATPG) technique to detect intra-portion faults. Inter-portion faults are detected by first forming a scan...
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7555689 |
Generating responses to patterns stimulating an electronic circuit with timing exception paths
Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit design having timing exception paths by more accurately determining the unknown values that...
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7555688 |
Method for implementing test generation for systematic scan reconfiguration in an integrated circuit
A method for implementing test generation for systematic scan reconfiguration in an integrated circuit is presented. The method may comprise: defining at least one set of detectable faults; setting...
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7550995 |
Method and system for using boundary scan in a programmable logic device
A programmable logic device for transferring JTAG scan data to a target device is disclosed. The programmable logic device includes a JTAG logic that communicates with a JTAG scan chain and...
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7552370 |
Application specific distributed test engine architecture system and method
An Application Specific Distributed Test Engine (ASDTE) that provides an optimized set of test resources for a given application. The test engine resources, configuration, functionality, and even...
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7552373 |
Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit...
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7546502 |
1114.9 tap linking modules
IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry...
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7546561 |
System and method of state point correspondence with constrained function determination
A system and method for determining scan chain correspondence including defining a reference scan chain having reference latches and a reference constraint, each of the reference latches having a...
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7546501 |
Selecting test circuitry from header signals on power lead
The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure,...
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7546500 |
Slack-based transition-fault testing
A system that generates test patterns for detecting transition faults in an integrated circuit (IC). During operation, the system receives slack times for each net in the IC. Note that a slack time...
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7546503 |
Selecting between tap/scan with instructions and lock out signal
A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port...
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7543206 |
Method for testing semiconductor integrated circuit and method for verifying design rules
A method is provided for testing a semiconductor integrated circuit by utilizing a scan path circuit provided to detect the degeneracy fault in the semiconductor integrated circuit, and bringing...
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7543207 |
Full scan solution for latched-based design
A full-scan latch is provided that may be used to incorporate design for test functionality in an integrated circuit. The full-scan latch includes a shadow latch, a multiplexer, and a slave latch....
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7543204 |
Method, apparatus and computer program product for designing logic scan chains for matching gated portions of a clock tree
Methods, apparatus, and computer program product are provided for designing logic scan chains for matching gated portions of a clock tree. A clock tree includes a plurality of sections, each...
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7543203 |
LSSD-compatible edge-triggered shift register latch
A shift register latch (SRL) ( 300, 304, 400 ) compatible with performing level sensitive scan design (LSSD) testing with a single scan clock (SCAN CLK) and single scan clock tree ( 64 ). The SRL...
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7543205 |
Control signal synchronization of a scannable storage circuit
A system of control signal synchronization of a scannable storage circuit includes any number of storage circuits interconnected together with logic circuitry to form at least a portion of a...
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7539957 |
Automatic test pattern generation tool with feedback path capabilities for testing circuits with repeating blocks
Methods and apparatus for testing integrated circuits are provided. Integrated circuits sometimes contain repeating blocks of identical circuitry. Each identical circuit block contains scan chain...
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7539913 |
Systems and methods for chip testing
Circuit and method for testing digital logic circuit modules of an integrated circuit chip. The circuit includes a storage device, a first multiplexing module and a selection device. The storage...
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7539915 |
Integrated circuit testing using segmented scan chains
An integrated circuit, and associated method and computer program, comprises a first scan chain portion comprising a plurality of first storage elements to interconnect in series according to a...
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7536616 |
JTAG testing arrangement
JTAG test equipment arranged to establish an asynchronous data transmission connection with a JTAG-compatible device under test for the transmission of test data between test access ports (TAP) in...
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7533315 |
Integrated circuit with scan-based debugging and debugging method thereof
An integrated circuit comprises a test interface, an embedded in-circuit emulator, a circuit-under-debugging, and a memory. The embedded in-circuit emulator is used for software debugging via the...
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7529294 |
Testing of multiple asynchronous logic domains
A digital system and a method for operating the same. The digital system includes (a) a first and a second pins, (b) first and second logic domains, and (c) first and second test pulse generator...
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7529997 |
Method for self-correcting cache using line delete, data logging, and fuse repair correction
An apparatus and method for protecting a computer system from array reliability failures uses Array Built-In Self-Test logic along with code and hardware to delete cache lines or sets that are...
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7526696 |
Scan-based self-test structure and method using weighted scan-enable signals
A scan-based self-test architecture and method using weighted scan enable signals is disclosed. The self-test architecture comprises: a linear feedback shift register; a phase shifter connected to...
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7526692 |
Diagnostic interface architecture for memory device
A diagnostic interface architecture for a memory device supports in one aspect one or more dynamically reconfigurable functional interconnects normally utilized in connection with reading data from...
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7526695 |
BIST with generator, compactor, controller, adaptor, and separate scan paths
A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102 , compactor 106 ,and controller 110 remain the same as in the known art. The changes between the...
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7526691 |
System and method for using TAP controllers
A system and method for dynamically writing to and reading from an internal register space of a chip using a TAP controller without interfering with the normal operation of the chip is provided....
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7525305 |
Core wrappers with input and output linking circuitry
A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores...
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7523370 |
Channel masking during integrated circuit testing
During testing of an integrated circuit (IC), a channel masking capability is used for masking out unknown or unpredictable (X) values from being compressed into a signature register. The approach...
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7519884 |
TAM controller for plural test access mechanisms
A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and...
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7519880 |
Burn-in using system-level test hardware
A burn-in test system. A burn-in test system includes a device under test (DUT), a temperature controller coupled to the DUT, and a test controller. During testing, the test controller: (a) sets a...
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7519889 |
System and method to reduce LBIST manufacturing test time of integrated circuits
A method to reduce logic built in self test manufacturing test time of integrated circuits, comprising: loading a plurality of test seeds in bulk into a locally accessible on-chip memory array...
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7519883 |
Method of configuring a system and system therefor
A first scan data is received at a first scan chain and a representation of the first scan data is subsequently provided from the first scan chain to a second scan chain to test the second scan...
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7516381 |
Integrated circuit test system
A test pattern compressed by an algorithm allowing real-time expansion of data corresponding to each of pins of an LSI is stored in a pattern memory of a pattern generator. A frame processor...
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7516378 |
Internal core connected to bond pads by distributor and collector
Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and...
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7516377 |
System and method for testing an on-chip initialization counter circuit
An apparatus and method is disclosed for providing automated testing for an on-chip initialization counter circuit that comprises a plurality of counter flip-flop circuits that are used in the...
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7516376 |
Test pattern generator, test circuit tester, test pattern generating method, test circuit testing method, and computer product
A test circuit tester includes a scan-chain input-output information generator that generates information for an input and an output of the scan chain that is scan-chain input-output information,...
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7512853 |
***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Semiconductor integrated circuit and method for testing the same
In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply...
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7512851 |
Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit
A method and apparatus time-division demultiplexes and decompresses a compressed input stimulus provided at a selected data rate R1, into a decompressed stimulus, driven at a selected data rate R2,...
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