Matches 601 - 650 out of 1005 < 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 >
Match Document Document Title
6463561 Almost full-scan BIST method and system having higher fault coverage and shorter test application time  
An almost full-scan method and system for detecting faults in circuits can achieve higher fault coverages and significantly shorter test application time as compared with full-scan techniques. A...
6457151 Waveform controller for an IC tester  
A waveform controller for an IC tester includes selectors and OR circuits for incorporating an edge of a strobe signal into a driver signal system and allows the use of the edge of the strobe...
6457149 Semiconductor integrated circuit and semiconductor integrated circuit test method  
With this invention, operation testing can be performed using general operation and emulation operation. With the MPU of this invention, using emulation operation, commands for transferring data...
6453436 Method and apparatus for improving transition fault testability of semiconductor chips  
A scan chain latch circuit is provided. The scan chain latch circuit includes a first shift register latch, a second shift register latch, and a third shift register latch. A first multiplexor is...
6449576 Network processor probing and port mirroring  
A method and system for systematically accessing and monitoring operating parameter signals within an IC device. A probe configuration logic selects a subset of signals from among a set of...
6442720 Technique to decrease the exposure time of infrared imaging of semiconductor chips for failure analysis  
The present invention can include a method and system for testing IC chips, including the steps of performing a binary search to a first failing pattern, determining a failing sink latch,...
6442721 Accelerating scan test by re-using response data as stimulus data  
A data summing scan cell includes an exclusive OR gate, a multiplexer and a flip-flop connected in series. Serial input data is input to one of three inputs of the multiplexer and serial output...
6427216 Integrated circuit testing using a high speed data interface bus  
The use of a JTAG port for boundary scan testing of integrated circuits, (IC) thereby allowing for the testing of the IC's after they have been mounted onto a circuit board. The present invention...
6427217 System and method for scan assisted self-test of integrated circuits  
A system and method for testing an integrated circuit (IC) by using a boundary scan ring having registers coupled to a functional scan ring having registers within the integrated circuit in order...
6415403 Programmable built in self test for embedded DRAM  
In the present invention a built in self test (BIST) for an embedded memory is described. The BIST can be used at higher levels of assembly and for commodity memories to perform functional and AC...
6415404 Method of an apparatus for designing test facile semiconductor integrated circuit  
In a method of designing a test facile semiconductor integrated circuit with scan paths, a method of designing an optimum assigning arrangement of scan paths. For minimizing an area of...
6415405 Method and apparatus for scan of synchronized dynamic logic using embedded scan gates  
A method and apparatus for random-access scan of a network of dynamic logic or N-nary logic, wherein the network includes sequentially clocked precharge logic gates and one or more scan gates is...
6412085 Method and apparatus for a special stress mode for N-NARY logic that initializes the logic into a functionally illegal state  
The present invention is a method and apparatus that initializes N-NARY logic and dynamic logic to a special stress mode. The present invention has a logic circuit that includes a shared logic tree...
6393593 Tester and method for testing LSI designed for scan method  
In a dc test, a plurality of dc test devices are connected to a plurality of tester pins, respectively and, in a function test, a function test device is connected to the plurality of tester pins.
6393591 Method for remotely testing microelectronic device over the internet  
The Internet is used to test an integrated circuit chip that is provided with boundary scan circuitry and plugged into a circuit board at a customer's location. A host computer at the...
6389566 Edge-triggered scan flip-flop and one-pass scan synthesis methodology  
An improved scan flip-flop and method of using same. The scan flip-flop has a separate dedicated scan output driven by a scan output signal driver. Scan shift race conditions are minimized by...
6385749 Method and arrangement for controlling multiple test access port control modules  
An arrangement controls an IC designed with multiple “core” circuits, such as multiple CPUs, with each core circuit including its own TAP controller. According to one example embodiment,...
6380724 Method and circuitry for an undisturbed scannable state element  
A method and circuitry for an undisturbed scannable state element. A scannable state element, implemented in a scan chain for testing an integrated circuit, includes both a dual-ported flop circuit...
6378093 Controller for scan distributor and controller architecture  
Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of...
6378108 Parity checking circuit  
A circuit for checking the parity of the contents of a register is provided. The register has a test mode in which a scan input of each flip-flop in the register is connected to a scan output of a...
6378095 Dual mode memory for IC terminals  
An electronic integrated circuit includes a signal path connected between the functional logic ( 15 ) thereof and an external output terminal thereof, which signal path includes a memory circuit (...
6370662 Modifying circuit designs running from both edges of clock to run from positive edge  
A system and method for increasing test coverage of digital integrated circuits is provided. Clock trees are examined and circuits modified to provide for a greater number of flip-flops operating...
6370663 Semiconductor integrated circuit  
A semiconductor integrated circuit comprises a first circuit block constituting an input circuit, a second circuit block constituted of a predetermined function block, a third circuit block...
6370664 Method and apparatus for partitioning long scan chains in scan based BIST architecture  
A technique is provided for testing an IC which includes a plurality of flip-flops. The flip-flops are arranged in at least one scan chain. The testing technique of the invention is practiced by...
6363501 Method and apparatus for saving and loading peripheral device states of a microcontroller via a scan path  
A microcontroller has many internal peripheral devices. The peripheral devices are coupled to a scan path. A memory storage device that is external to the microcontroller is also coupled to the...
6363510 Electronic system for testing chips having a selectable number of pattern generators that concurrently broadcast different bit streams to selectable sets of chip driver circuits  
A system for testing integrated circuit chips is comprised of a selectable number of pattern generators, each of which is coupled via a separate bus to a selectable number of chip driver circuits....
6363505 Programmable control circuit for grounding unused outputs  
A circuit for programmably grounding (or coupling to the positive rail) unused outputs to improve noise immunity of the circuit. The circuit of the present invention achieves, for example,...
6363504 Electronic system for testing a set of multiple chips concurrently or sequentially in selectable subsets under program control to limit chip power dissipation  
A system for testing integrated circuit chips includes a signal generator which generates a clock signal; and a sequential control circuit having a first input which receives the clock signal, a...
6353904 Method of automatically generating new test programs for mixed-signal integrated circuit based on reusable test-block templates according to user-provided driver file  
A method of automatically generating a mixed-signal test program. The method according to one embodiment of the present invention is implemented in software in the form of two software processes....
6351836 Semiconductor device with boundary scanning circuit  
Provided is a semiconductor device capable of performing a function test and a DC test including an output voltage test every time a test jig is sequentially caused to come in contact with pads of...
6343358 Executing multiple debug instructions  
Apparatus for processing data is provided, said apparatus comprising: a main processor 4 ; an instruction transfer register ITR for holding a data processing instruction and accessible via a first...
6343365 Large-scale integrated circuit and method for testing a board of same  
In a large-scale integrated circuit, a scan path is divided between an I/O scan path that is formed by a series connection between only flip-flops that are in a region near an I/O pin and an...
6341361 Graphical user interface for testability operation  
A graphical user interface (GUI) provides a design engineer the capability of automatically inserting scan logic and test logic into a design. The graphical user interface includes a scan insertion...
6341092 Designing memory for testability to support scan capability in an asic design  
A system and method are presented for incorporating boundary scan test capability in an embedded memory. Existing half-latches within the memory are augmented to create full-latches, configurable...
6334198 Method and arrangement for controlling multiply-activated test access port control modules  
An arrangement controls an IC designed with multiple "core" circuits, such as multiple CPUs, with each core circuit including its own TAP controller and with multiple TAP controllers enabled at a...
6330698 Method for making a digital circuit testable via scan test  
The method for modifying a representation of a digital circuit (102) in order to allow a scan test comprises a step (106) for selecting a number of the memory elements of the circuit to be made...
6327685 Logic built-in self test  
A BIST method that modifies the scan chain path and scan clocks to allow for distributed BIST test. In this distributed BIST concept, the Linear Feedback Shift Register (LFSR) and the Multiple...
6327683 Device scan testing  
A circuit and method for scan testing some or all connections to a device, the device under test having at least one output and a plurality of inputs greater than the number of outputs. Such a...
6324614 Tap with scannable control circuit for selecting first test data register in tap or second test data register in tap linking module for scanning data  
A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).
6324664 Means for testing dynamic integrated circuits  
A test circuit that includes a scan path having serially coupled scan flip-flops clocked by a system clock signal, an index counter clocked by the system clock for providing an index output for...
6321354 Testable circuit with a low number of leads  
The present invention relates to an electronic device of the "SMARTCARD" type including a single input/output lead for communicating with the microcontroller from the outside. Interface registers...
6321329 Executing debug instructions  
Apparatus for processing data is provided, said apparatus comprising: a main processor 4 driven by a main processor clock signal clk at a main processor clock frequency; debug logic 6, 12 at least...
6314486 Data transfer with JTAG controller using index register to specipy one of several control/status registers for access in read and write operations with data register  
A system for accessing control and status registers for a device within a computer system. These control and status registers are used to control and configure the device and to read status...
6314039 Characterization of sense amplifiers  
A circuit and method characterizes a sense amplifier, such as the type utilized in computer memory systems. The sense amplifier characterization circuit comprises a sense amplifier having one or...
6311302 Method and arrangement for hierarchical control of multiple test access port control modules  
An arrangement controls an IC designed with multiple "TLM'ed core" circuits, such as multiple CPUs, with each core circuit including its own TAP controller and with multiple TAP controllers enabled...
6304987 Integrated test circuit  
A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first...
6304988 Scan testable circuit arrangement  
A circuit arrangement utilizes a common bus for functional operations of logic circuits and for scan testing the logic circuits. In one embodiment, input/output ports and scan test ports of the...
6292915 Method of design for testability and method of test sequence generation  
The invention provides a method of design for testability at RTL which can guarantee high fault coverage and a method of test sequence generation for easily generating test sequences for an RTL...
6289477 Fast-scan-flop and integrated circuit device incorporating the same  
Disclosed is a scan-flop adapted for use in testing integrating of an integrated circuit's core logic and an integrated circuit device incorporating the same. Broadly, the scan-flop comprises a...
6289480 Circuitry for handling high impedance busses in a scan implementation  
An integrated circuit implemented utilizing scan design for test techniques includes a plurality of bus driver circuits. Each bus driver circuit has a driver output connected to a bus to provide an...
Matches 601 - 650 out of 1005 < 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 >