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6611934 |
Boundary scan test cell circuit
A test cell ( 12 ) provides boundary scan testing in an integrated circuit ( 10 ). The test cell ( 12 ) comprises two memories, a flip-flop ( 24 ) and a latch ( 26 ), for storing test data. A first...
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6611941 |
Method for RAMDAC testing
A method of testing a plurality of registers in a RAMDAC, each of the registers having a plurality of bits. First, the bits of the registers are all reset to a first logic state. Then, one logic...
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6611933 |
Real-time decoder for scan test patterns
A method and apparatus for improving the efficiency of scan testing of integrated circuits is described. This efficiency is achieved by reducing the amount of required test stimulus source data and...
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6606720 |
Scan structure for CMOS storage elements
Scan chain links which step data through a scan chain using only a single control signal, and which require a reduced number of transistors to scan data into and out of a latch. One scan chain...
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6606736 |
Computer-aided timing adjusting method and apparatus
Input signal dull values in a targeted set-up error path are read from a delay information file, in this path, a cell in a proceeding stage of the cell with the largest input signal dull value is...
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6601202 |
Circuit configuration with deactivatable scan path
A circuit configuration with a deactivatable scan path, includes a number of function blocks each connected to at least one other of the function blocks. At least one sub-set of the connections is...
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6598192 |
Method and apparatus for testing an integrated circuit
A programmable clock generator ( 220 ), which is part of an integrated circuit (IC) ( 210 ), provides clock signals ( 230 ) and ( 232 ) to various components of the IC. The clock generator includes...
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6597164 |
Test bus circuit and associated method
An on-chip test bus circuit for testing a plurality of circuits and an associated method. The test bus circuit consists of a test bus and a plurality of switching circuits which selectably provide...
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6598191 |
Verification of asynchronous boundary behavior
A function for verifying an asynchronous boundary behavior of a digital system. The asynchronous boundary is formed at a coupling between a first series of registers clocked by a write clock (the...
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6591388 |
High speed sink/source register to reduce level sensitive scan design test time
Test data is provided through shift registers, operated at a high clock rate comparable to or exceeding a normal high speed clock rate of a chip being tested, to each of a plurality of scan chains...
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6591387 |
Communication equipment with boundary scan elements
A communication system includes a plurality of boundary scan elements including input and output terminals and a plurality of boundary cells individually assigned to the respective input terminals...
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6587813 |
PCI bus system testing and verification apparatus and method
An improved PCI verification method and apparatus provides iterative testing of all desired conditions or protocol combinations in a PCI system. One or more commands may be tested in combination...
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6587981 |
Integrated circuit with scan test structure
Scan path structures are provided for integrated circuits which contain one or more cores or levels of sub-cores embedded within the cores. Circuitry is provided to permit scan testing of scan...
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6581190 |
Methodology for classifying an IC or CPU version type via JTAG scan chain
A method in a data processing system for identifying a circuit. In a preferred embodiment, a set of bits, with a defined chain length, are shifted into the circuit one bit at a time. The bits...
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6578166 |
Restricting the damaging effects of software faults on test and configuration circuitry
A system that restricts the damaging effects of software faults that interact with test and configuration circuitry. This test and configuration circuitry includes a scan chain in the form of a...
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6574590 |
Microprocessor development systems
A procedure and processor are disclosed for avoiding lengthy delays in debug procedures during access by a memory mapped peripheral device. The processor includes in-circuit emulation means...
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6573703 |
Semiconductor device
A semiconductor for having a reduced required number of probes for inputting burn-in data to a target circuit, including two separate scan chains having respective first and second input terminals,...
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6571363 |
Single event upset tolerant microprocessor architecture
A single-event-upset, fault-tolerant data processor architecture enables error detection and correction according to algorithms given. A hardware intensive solution compares signatures of two...
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6567942 |
Method and apparatus to reduce the size of programmable array built-in self-test engines
A programmable array built-in self test system for testing an embedded array allows self test functions, e.g. test patterns, read/write access, and test sequences, to be modified without hardware...
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6560737 |
Method for adding scan controllability and observability to domino CMOS with low area and delay overhead
Circuitry for scanning and observing domino CMOS logic or other logic gates. Master and slave stages includes circuitry for latching a bit into the master stage through pulsing of a clock signal...
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6560739 |
Mechanism for enabling compliance with the IEEE standard 1149.1 for boundary-scan designs and tests
A mechanism for enabling compliance with the IEEE boundary-scan standard 1149.1 includes, in a first preferred embodiment, a compliance enabler working with non-compliant embedded boundary-scan...
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6560738 |
Fault propagation path estimating method, fault propagation path estimating apparatus and recording media
A gate connected to an input side of a normal signal line estimated-as in a logical state equal to an expected value with an implication operation is detected as a newly implication-capable gate,...
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6556037 |
Semiconductor integrated circuit and test board
In a semiconductor integrated circuit, a test controller generates test patterns for all of the pins of a core logic from test patterns for only the pins necessary for the test. The test controller...
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6553524 |
Method for automating validation of integrated circuit test logic
A methodology for automatic validation of integrated circuit (IC) test hardware that is performed during extraction of the test hardware. Signal connectivity between output test ports of one or...
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6550031 |
Transparently gathering a chips multiple internal states via scan path and a trigger
A microcontroller has many miscellaneous logics. The miscellaneous logic can include input/outputs of combinational logic or peripheral devices of the microcontroller, storage devices such as...
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6546514 |
Integrated circuit analysis and design involving defective circuit element replacement on a netlist
A method of operating on a net-list describing an integrated circuit design for use with an automated test pattern generator for testing an integrated circuit built using the design is described....
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6539511 |
Semiconductor integrated circuit devices with test circuit
In a semiconductor integrated circuit device supporting a boundary scan test, the state of an I/O cell is set under the control of a DC test control circuit through a boundary scan register...
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6539508 |
Methods and circuits for testing programmable logic
Described is a test circuit that can be instantiated on a programmable logic device to perform at-speed functional tests of programmable resources, including internal memory and routing resources....
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6539507 |
Integrated circuit with alternately selectable state evaluation provisions
An integrated circuit incorporating test access provisions and a system addressable command control register; and provisions for selectably enabling and accessing one or the other for purposes of...
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6539497 |
IC with selectively applied functional and test clocks
A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry ordinarily operative together. Further...
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6536008 |
Fault insertion method, boundary scan cells, and integrated circuit for use therewith
A number of fault injection circuits and corresponding methods for injecting correlated, uncorrelated, non-persistent and persisting faults at the primary outputs of boundary scan cells are...
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6536007 |
Models and technique for automated fault isolation of open defects in logic
A method and system for diagnosing open defects in logic circuits. The method employs a pair of diagnostic fault models and an associated algorithm to automate the diagnoses of open...
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6535049 |
Multipurpose test chip input/output circuit
A system for testing an integrated circuit. The system includes a plurality of simultaneous switching output (SSO) cells with each of the plurality of simultaneous SSO cells including an output...
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6532571 |
Method to improve a testability analysis of a hierarchical design
A method to improve the testability and analysis of a hierarchical semiconductor chip design formed from a plurality of macros, each macro identifying a particular portion of a semiconductor chip...
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6529033 |
Area efficient clock inverting circuit for design for testability
A method for fabricating IC devices including both rising edge-triggered circuits (e.g., flip-flops or latches) and falling edge-triggered circuits in which a clock signal line is selectively...
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6530050 |
Initializing and saving peripheral device configuration states of a microcontroller using a utility program
A microcontroller has many internal peripheral devices. The peripheral devices have many registers that can be used to configure the peripheral devices for a particular application. The...
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6522985 |
Emulation devices, systems and methods utilizing state machines
An emulation device including a serial scan testability interface having at least first and second scan paths, and state machine circuitry connected and responsive to said second scan path...
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6516432 |
AC scan diagnostic method
Disclosed is an alternating current (AC) scan diagnostic system in which one or a plurality of scan chains are tested by serially propagating predetermined bit patterns through the scan chain and...
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6510535 |
Method of design for testability for integrated circuits
A method of design for testability using scan FF identification of this invention eases generation of test sequences as compared with conventional technique. An FF relation graph is generated from...
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6510534 |
Method and apparatus for testing high performance circuits
A method for at-speed testing high-performance digital systems and circuits having combinational logic and memory elements that may be both scannable and non-scannable is performed by enabling at...
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6507209 |
Tester accuracy using multiple passes
A test circuit generally comprising a tester connected to a socket for holding a device under test. The device may be configured to have (i) a first function and (ii) a final function. The tester...
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6499124 |
Intest security circuit for boundary-scan architecture
A security circuit for an IEEE Standard 1149.1 compliant PLD that is controlled by a security bit or bits programmed when the PLD is incorporated into a final product. The security circuit includes...
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6496030 |
Scan flip-flop providing both scan and propagation delay testing
A semiconductor integrated circuit device is provided with a selector that selects a normal operation signal or a circuit diagnosis input signal depending upon a first-mode input signal. A first...
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6490702 |
Scan structure for improving transition fault coverage and scan diagnostics
A scan chain latch circuit is provided. The scan chain latch circuit includes a first shift register latch and a second shift register latch. The scan chain latch circuit also includes a...
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6487688 |
Method for testing circuits with tri-state drivers and circuit for use therewith
A scan-testing method for circuits having tri-state bus drivers disables all drivers during scan intervals and enables at most one of the bus drivers during the capture interval. A driver select...
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6487682 |
Semiconductor integrated circuit
A semiconductor integrated circuit includes a semiconductor chip body, a plurality of input/output cells arranged on a surface of the semiconductor chip body at parts including a peripheral part...
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6484280 |
Scan path test support
Functional testing of complex digital integrated circuits. A complex integrated circuit such as a system-on-a-chip (SOC) designed using high-level tools is tested by decomposing it into functional...
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6484275 |
System and method for interfacing data with a test access port of a processor
A processor in accordance with the present invention includes memory that stores test data and control data. The processor also includes a test application that transmits the test data and the...
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6473727 |
Processor development systems
A processor including in-circuit emulation means comprising a plurality of scan chains of serially connected registers coupled to a means for enabling a serial scan procedure to be carried out, a...
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6467057 |
Scan driver of LCD with fault detection and correction function
A scan driver of LCD with fault detection and correction circuit is disclosed herein. The scan driver fabricated on a glass substrate locates at both ends of the scan buses can simultaneously drive...
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