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7620861 |
Method and apparatus for testing integrated circuits by employing test vector patterns that satisfy passband requirements imposed by communication channels
Embodiments of an apparatus and method for high-speed testing of a device under test are described herein, where the device under test is coupled to a tester via a limited passband communication...
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7620858 |
Fabric-based high speed serial crossbar switch for ATE
A loopback module is disclosed in which N differential High Speed Serial (HSS) digital data input channels are received and sent to a serial to parallel converter, whose output is M-bit wide...
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7617431 |
Method and apparatus for analyzing delay defect
The apparatus for analyzing a delay defect of the present invention obtains the RC of the maximal incidence among region codes (RCs) to which check circuits detecting errors caused with gradual...
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7617428 |
Circuits and associated methods for improved debug and test of an application integrated circuit
Circuits and associated methods for testing internal operation of an application integrated circuit. Features and aspects hereof add configurable test interrupt circuits to an application circuit...
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7617427 |
Method and apparatus for detecting defects in integrated circuit die from stimulation of statistical outlier signatures
A method and computer program for detecting and locating defects in integrated circuit die from stimulation of statistical outlier signatures includes receiving as input a test value of an...
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7613974 |
Fault detection method and apparatus
This invention relates to fault detection in electrical circuits. The invention provides a method and apparatus for testing an input circuit by generating a periodic test signal having a...
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7613971 |
Semiconductor integrated circuit with delay test circuit, and method for testing semiconductor integrated circuit
A semiconductor integrated circuit includes an input side flip-flop; a combinational circuit having an input connected with the input side flip-flop; an output side flip-flop connected with an...
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7613968 |
Device and method for JTAG test
In order to realize a JTAG test of a printed board including a semiconductor device having JTAG test unsupported input/output terminals inside thereof, one device is logically divided into two...
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7613966 |
Hyperjtag system including debug probe, on-chip instrumentation, and protocol
A system for simultaneously interfacing multiple test instruments with multiple processor cores includes an on-chip instrumentation, a probe, and a connection mechanism for providing a transmission...
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7613965 |
Apparatus and method for high-speed SAS link protocol testing
An apparatus for changing a connection between two serial components on the same circuit board. The apparatus comprises at least one column, and each column includes first, second, third and fourth...
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7613964 |
Relay device and corresponding method
The invention consists of a relay device including: at least one mode change device for changing the relay device from a normal mode to a test mode; an interface for receiving test script from a...
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7613963 |
Wireless method and apparatus for testing armament circuits
The testing apparatus of the present invention provides a self-contained test module that connects to the weapons firing circuit on the weapons platform. This test module communicates with a data...
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7612698 |
Test apparatus, manufacturing method, and test method
There is provided a test apparatus for testing a device under test, the test apparatus including: a test signal supplying section that supplies a digital input signal for testing purposes, to the...
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7610538 |
Test apparatus and performance board for diagnosis
A test apparatus being capable of replacing a test module with the other kind of test module that tests device under tests by using the test module is provided. The test apparatus includes a...
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7610535 |
Boundary scan connector test method capable of fully utilizing test I/O modules
Read the description file of a PCBA without determining and selecting connectors which might be relevant to boundary scan. The description file of the PCBA determines which pins of the connectors...
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7610532 |
Serializer/de-serializer bus controller interface
An application specific integrated circuit (ASIC) uses a dedicated interface between core logic and an independent Serializer/De-serializer bus (SBus) to provide SBus capabilities to the core...
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7610531 |
Modifying a test pattern to control power supply noise
Mechanisms for modifying a test pattern to control power supply noise are provided. A portion of a sequence of states in a test sequence of a test pattern waveform is modified so as to achieve a...
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7610530 |
Test data generator, test system and method thereof
A test data generator, test system and method thereof are provided. In the example method, parallel test data may be received at a first data rate. The received parallel test data may be converted...
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7610529 |
Testing mobile wireless devices during device production
A system and method of testing a wireless communication device during device production comprises designating as a data log buffer when the device is being produced, at least part of random access...
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7610528 |
Configuring flash memory
A system for configuring or testing memory may cycle a memory array while substantially concurrently performing other functional testing. In particular implementations, the system may configure, or...
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7610527 |
Test output compaction with improved blocking of unknown values
Implementations of the present principles are directed to test output compaction arrangements and a methods of generating control patterns for unknown blocking. The specified bits in the control...
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7610526 |
On-chip circuitry for bus validation
Systems, methodologies, media, and other embodiments associated with validating a bus are described. One exemplary system embodiment includes an integrated circuit operably connectable to a bus,...
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7610520 |
Digital data signal testing using arbitrary test signal
For testing a digital data signal, a value derived from the digital data signal at a sampling point is compared against a corresponding value of an arbitrary test signal. The comparison is...
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7607057 |
Test wrapper including integrated scan chain for testing embedded hard macro in an integrated circuit chip
An apparatus and method are disclosed for testing a hard macro that is embedded in a system on a chip (SOC) that is included in an integrated circuit chip. The SOC includes the hard macro. A logic...
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7607056 |
Semiconductor test apparatus for simultaneously testing plurality of semiconductor devices
Disclosed herein is a semiconductor test apparatus for simultaneously testing a plurality of semiconductor devices. The semiconductor test apparatus includes a plurality of pattern generation...
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7607055 |
Semiconductor memory device and method of testing the same
A semiconductor memory device includes at least one first built in self test (BIST) circuit configured to generate test pattern data, and at least one second BIST circuit configured to receive the...
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7606696 |
Programmable extended compression mask for dynamic trace
This invention provides trace address compression by comparing respective bytes of a current trace address with a stored comparison address. Only the least significant bytes of the current trace...
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7603603 |
Configurable memory architecture with built-in testing mechanism
A configurable memory architecture includes a built-in testing mechanism integrated in said memory to support very efficient built-in self-test in Random Access Memories (RAMs) with greatly reduced...
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7603598 |
Semiconductor device for testing semiconductor process and method thereof
A semiconductor device for testing a semiconductor process applied to manufacturing the semiconductor device is disclosed. The semiconductor device includes at least a testing group. The testing...
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7603497 |
Method and apparatus to launch write queue read data in a microprocessor recovery unit
A method of checkpointing a microprocessor by providing, in parallel, a current read value from a queue and a next read value from the queue, and then selectively passing one of the current read...
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7602171 |
System for testing memory modules using a rotating-type module mounting portion
A system for testing memory modules having a rotating-type board mounting portion with a plurality of mounting surfaces positioned at different planes and connected around an axis to form a...
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7600167 |
Flip-flop, shift register, and scan test circuit
A flip-flop has a first latch and a second latch. The first latch has a first feedback circuit and a first selecting circuit which selects one of a first data input signal and an output signal of...
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7599826 |
System and method for generating various simulation conditions for simulation analysis
A system for generating various simulation conditions for simulation analysis is disclosed. The system includes: a signal generating module ( 301 ) for generating an N-bit binary sequence...
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7596731 |
Test time reduction algorithm
Exemplary embodiments provide a method and system for reducing test time for electronic devices. The method and system aspects include receiving a test data file containing results from a set of...
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7596730 |
Test method, test system and assist board
A test method for testing a device under test by using an event tester is provided. The test method includes: receiving a test signal generated by the event tester and applied to the device under...
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7596729 |
Memory device testing system and method using compressed fail data
A memory device testing system includes a signal generator providing memory command, address and write data signal to write data in a memory device and then read the data from the memory device....
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7596173 |
Test apparatus, clock generator and electronic device
There is provided a clock generator for generating a single-phase clock into which jitter has been injected, having a multi-phase clock generating section for generating a plurality of clock...
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7595467 |
Fault detection system and method for managing the same
A fault detection system comprises a data server configured to collect parameters incoming from at least one apparatus, at least one fault-sensing module configured to generate an alarm signal if...
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7594150 |
Fault-tolerant architecture of flip-flops for transient pulses and signal delays
A method and apparatus for a structure of a flip-flop that is tolerant to the noise pulses occurring due to the presence of crosstalk faults by sampling the input data multiple times before and...
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7590911 |
Apparatus and method for testing and debugging an integrated circuit
An integrated circuit includes a first deserializer that deserializes serial data containing at least one of test instructions and/or data in a first format. A monitor module communicates with the...
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7590904 |
Systems and methods for detecting a failure event in a field programmable gate array
An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA...
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7590903 |
Re-configurable architecture for automated test equipment
An adaptive test system includes one or more reconfigurable test boards, with each test board including at least one re-configurable test processor. The re-configurable test processors can transmit...
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7590902 |
Methods and apparatuses for external delay test of input-output circuits
Various methods and apparatuses are described for a system that includes some on-chip components, e.g., I-Os, test processors, soft wrappers, etc., an external testing unit that provides Parametric...
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7590901 |
Apparatus, system, and method for dynamic recovery and restoration from design defects in an integrated circuit
An apparatus, system, and method are disclosed for the recovery from a design defect in an integrated circuit. The apparatus includes an error check module, a control settings module, a retry...
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7590900 |
Flip flop circuit & same with scan function
A pulse-based flip flop, which outputs a scan input signal and a data signal, may include: a pulse generator to generate a pulse signal for coordinating operation of the flip flop; a multiplexer to...
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7590891 |
Debugging circuit and a method of controlling the debugging circuit
In a debugging circuit and a controlling method of the debugging circuit, a mode judgment signal is generated which indicates that a central processing unit (CPU) is preparing to debug a...
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7587649 |
Testing of reconfigurable logic and interconnect sources
Methods and systems for verifying the proper function of reconfigurable logic elements and reconfigurable interconnects are disclosed. Reconfigurable logic elements in an emulation integrated...
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7587642 |
System and method for performing concurrent mixed signal testing on a single processor
The present application describes a system and method for testing semiconductor devices and specifically for testing mixed signal semiconductor devices. The test systems are configured to test the...
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7584392 |
Test compaction using linear-matrix driven scan chains
A scan technique using linear matrix to drive scan chains is used, along with an ATPG, to constraint scan test vectors to be generated through the linear matrix. The linear matrix scan technique...
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7584390 |
Method and system for alternating between programs for execution by cells of an integrated circuit
A method and device for data processing in an integrated circuit having cells, the cells adapted for executing programs. A first program is run. In response to a waiting condition during which no...
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