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7478300 Method for testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device  
A method for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device is provided. With the method, each clock domain has its own scan paths that do not...
7478304 Apparatus for accelerating through-the-pins LBIST simulation  
The present invention provides an apparatus and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a...
7478287 Semiconductor integrated circuit and electronic device  
A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a...
7478293 Method of securing the test mode of an integrated circuit via intrusion detection  
An electronic circuit, including: a logic circuit having a plurality of logic cells; storage cells able to form a shift register, able to be connected to the logic cells; a connection control...
7478294 Time controllable sensing scheme for sense amplifier in memory IC test  
A test method is described in which a signal from a tester enters a memory chip or memory module into a special test mode. The special test mode allows leakage defects connected to bit lines to be...
7475302 Decoded match circuit for performance counter  
A match circuit connected to a bus carrying data is described. In one embodiment, the match circuit includes logic for activating a decoded_match signal, the logic for activating a decoded match...
7475304 Bit error tester  
A method and device for comparing two generic digital signals over a wide range of data rates and for counting the number of bit errors between digital signals under the conditions of noise and...
7475311 Systems and methods for diagnosing rate dependent errors using LBIST  
Systems and methods for performing logic built-in self-tests (LBISTs) to detect “at-speed” errors in a digital circuit. In one embodiment, an input bit pattern is propagated through target...
7474974 Embedded time domain analyzer for high speed circuits  
A method of providing an on-chip high-speed time domain digital analyzer for the characterization and analysis of signals within an integrated circuit is provided. The method involves processing...
7475305 Method of high speed data rate testing  
A method to optimize a data strobe for a multiple circuit, automatic test system is achieved. The method comprises, first, probing, in parallel, a circuit group wherein the circuit group comprises...
7475313 Unique pBIST features for advanced memory testing  
This invention is new built-in self test instructions. A pointer register stores data identifying one bit of a data register. That bit determines whether the data of another data register is used...
7475303 HyperJTAG system including debug probe, on-chip instrumentation, and protocol  
A system for simultaneously interfacing multiple test instruments with multiple processor cores includes an on-chip instrumentation, a probe, and a connection mechanism for providing a transmission...
7475328 Loop status monitoring apparatus  
A loop status monitoring apparatus monitors a status of an arbitration loop that includes a plurality of devices and a switch that controls connections between the devices, has at least one of loop...
7475301 Increment/decrement circuit for performance counter  
An increment/decrement circuit for use with a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. In one embodiment, the increment/decrement circuit includes a...
7472320 Autonomous self-monitoring and corrective operation of an integrated circuit  
Disclosed is a method and apparatus for autonomously self-monitoring and self-adjusting the operation of an integrated circuit device throughout the integrated circuit device's useful life. The...
7472322 On-chip interface trap characterization and monitoring  
A method and apparatus for testing semiconductor wafers is disclosed in which a test circuit is used that includes a waveform generator. The test circuit can test a single transistor or can test...
7472323 Mechanism to stop instruction execution at a microprocessor  
A method and apparatus for stopping the internal clock of a microprocessor synchronously with the execution of an instruction is provided. A stop instruction is placed in a sequence of instructions...
7472321 Test apparatus for mixed-signal semiconductor device  
A test apparatus for a mixed-signal semiconductor device that includes a plurality of event tester modules including analog and digital signal tester boards, a test head for event tester modules, a...
7469370 Enabling multiple testing devices  
A method for enabling multiple testing devices within a system. The method may include determining whether a first testing device or a second testing device is coupled to the system. Provided the...
7467340 TAP, ST, lockout, and IR SO enable output data control  
Two common varieties of test interfaces exist for ICs and/or cores, the IEEE 1149.1 Test Access Port (TAP) interface and internal scan test ports. The TAP serves as a serial communication port for...
7467339 Semiconductor integrated circuit and a method of testing the same  
A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set...
7464314 Method for validating an integrated circuit and related semiconductor product thereof  
A method for converting an integrated circuit into a test circuit for validating functionality of the integrated circuit is disclosed. The integrated circuit is formed on a wafer, and includes a...
7464310 Programmable state machine of an integrated circuit  
A programmable state machine of an application specific integrated circuit (ASIC) is programmed by enabling the scan mode of the integrated circuit. The process of programming the state machine...
7461312 Digital signature generation for hardware functional test  
A Multiple Input Shift Register (MISR) is used to generate signatures, based on data from a device under test, in order to validate the proper sequence and content of the data over a defined period...
7461309 Systems and methods for providing output data in an LBIST system having a limited number of output ports  
Systems and methods for performing logic tests in digital circuits with means for segmentation and output of data through limited I/O ports. In one embodiment, a system includes test circuitry...
7461308 Method for testing semiconductor chips by means of bit masks  
A method for testing semiconductor chips is disclosed. In one embodiment, a chip to be tested which has a test logic, at least one test mode is set, the test modes are executed in the chip and test...
7461311 Device and method for creating a signature  
A device and a method for forming a signature, a predefined number of shift registers being provided, to which input data to be tested is applied bit-by-bit and in parallel as successive data words...
7457992 Delay fault test circuitry and related method  
The invention provides for a delay fault test circuitry for producing a train of two clock pulses in response to two respective clock signals of different frequency associated with logic circuits...
7457998 Scan register and methods of using the same  
An improved scan register and methods of using the same have been disclosed. In one embodiment, the improved scan register includes a master latch having a data input, a data output, and a control...
7454674 Digital jitter detector  
In one embodiment, a jitter detector comprises a logic circuit coupled to receive a plurality of inputs indicative of states captured from a plurality of outputs of a delay chain responsive to a...
7454676 Method for testing semiconductor chips using register sets  
A method for testing semiconductor chips having a test logic unit includes: providing a chip having n different register sets, each of which has m different registers that are subdivided into m...
7454679 Test apparatus, computer readable program for test apparatus, test pattern recording medium, and method for controlling test apparatus  
A test apparatus for testing a device under test includes a plurality of conversion processing units for converting split patterns recorded respectively on different split pattern recording...
7451368 Semiconductor device and method for testing semiconductor device  
A packaged semiconductor device that enables testing of semiconductor chips incorporated therein in a simplified and efficient manner. The semiconductor device includes a packaged logic chip for...
7447960 Method of efficiently loading scan and non-scan memory elements  
The present invention provides a method and apparatus for efficiently loading values into scan and non-scan memory elements. First, the network used to distribute control signals to the memory...
7447966 Hardware verification scripting  
Exemplary techniques for verifying a hardware design are described. In a described embodiment, a method comprises compiling an error verification object corresponding to an error verification...
7447956 Method and apparatus for testing data steering logic for data storage having independently addressable subunits  
Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to...
7447958 Parallel input/output self-test circuit and method  
A parallel data transmission test system can include a receiver section ( 100 ) having input selector circuits ( 104 -O to 104 -N) that provide a received test data to logic adjust circuits ( 106...
7444575 Architecture and method for testing of an integrated circuit device  
In one embodiment, the present invention provides a platform of hardware and/or software that enables the complete access and reliable testing of multiple integrated circuit (IC) devices within a...
7444570 Apparatus and method for controlling frequency of an I/O clock for an integrated circuit during test  
A test system including a device under test (DUT) and a tester, where the DUT includes I/O interface logic and a clock circuit. The clock circuit includes a core clock circuit, a pad clock circuit,...
7444573 VLCT programmation/read protocol  
An integrated circuit with built-in self test enables internal data registers to be written to or read from via an external tester. In a command phase the programmable built-in self test unit...
7444574 Stimulus extraction and sequence generation for an electric device under test  
A method and system that utilizes a graphical interface that enables a user to select and capture building blocks of a Device Under Test (DUT) test scenario from a previously run test case or from...
7444558 Programmable measurement mode for a serial point to point link  
A serial point to point link that communicatively couples an integrated circuit (IC) device to another IC device is initialized by transferring a training sequence of symbols over the link....
7441168 Fault detecting method and layout method for semiconductor integrated circuit  
The present invention provides a fault detecting method and a layout method for a semiconductor integrated circuit. The fault detecting method performs detection for faults in a semiconductor...
7441169 Semiconductor integrated circuit with test circuit  
A semiconductor integrated circuit has a scan path that includes, between the output of the first logic section and the input of the functional block, a parallel path and a serial shift path for...
7437261 Method and apparatus for testing integrated circuits  
A distributed operating system for a semiconductor test system, such as automated test equipment (ATE), is described. The operating system includes a host operating system for enabling control of...
7437258 Use of I2C programmable clock generator to enable frequency variation under BMC control  
The present invention provides systems and methods for performing frequency margin testing of a computer system, such as a server. A system of the invention can include a controller, e.g., a BMC,...
7437643 Automated BIST execution scheme for a link  
Training of a link is performed, wherein the link is an interconnect between two devices of a computer system. A built-in self-test (BIST) of the link is performed. A result from the link training...
7437635 Testing hard-wired IP interface signals using a soft scan chain  
A set of boundary scan registers are implemented by reconfiguring the functional blocks of a reconfigurable device. This “soft-wired” set of boundary scan registers can be used to test the...
7437638 Boundary-Scan methods and apparatus  
Disclosed herein are various methods and apparatus related to Boundary-Scan testing, including a method for generating Boundary-Scan test vectors. The method assigns different binary signatures to...
7434125 Integrated circuit, test system and method for reading out an error datum from the integrated circuit  
An integrated circuit is provided, the integrated circuit having a test circuit for reading out an error datum from the integrated circuit in accordance with a test mode, wherein the error datum is...
Matches 201 - 250 out of 1709 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >