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7516375 |
Methods and systems for repairing an integrated circuit device
Provided are systems for repairing an integrated circuit device. The systems include detection logic configured to locate a defective portion of an integrated circuit device, a supplemental...
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7516383 |
Method and apparatus for analyzing delay in circuit, and computer product
An extracting unit extracts unprocessed capturing destination in a circuit. A tracing unit traces an output branch point from a capturing destination and a determining unit determines an estimated...
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7514951 |
Negative voltage noise-free circuit for multi-functional pad
A circuit and a method are provided to produce a noise-free multi-input I/O pad for an integrated circuit chip. The circuit includes a normal mode internal node, which connects to normal mode...
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7512872 |
Test apparatus and test method
The apparatus includes a first variable delay circuit that delays a data signal from a device under test (DUT) to output a delay data signal; a second variable delay circuit that delays a clock...
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7512850 |
Checkpointing user design states in a configurable IC
Some embodiments provide a configurable integrated circuit (IC) that has several configurable circuits and several user design state (UDS) circuits. The UDS circuits store user-design state values....
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7509547 |
System and method for testing of interconnects in a programmable logic device
Methods and systems provide for early and simplified testing for defects in the interconnects of a programmable logic device (PLD) and in associated software tools. Data that describes the...
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7509549 |
Dynamic frequency scaling for JTAG communication
A system comprising a system under test (SUT) having a control logic. The SUT further comprises testing logic coupled to the SUT and adapted to provide to the SUT a clock signal to facilitate...
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7506229 |
Method and system for optimizing an integrated circuit
A method and system for optimizing an integrated circuit is described. The method includes generating ( 102 ) a characteristic table of the integrated circuit. The method further includes selecting...
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7506230 |
Transient noise detection scheme and apparatus
A method, system and apparatus for detecting soft errors in non-dataflow circuits. In a preferred embodiment, input is received at a latch system. The latch system consists of two pairs of latches....
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7506228 |
Measuring the internal clock speed of an integrated circuit
A system and methods to transfer data between a testing interface and an IC. The system may include a synchronization subsystem to monitor the transitions of the test interface clock and/or IC...
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7506227 |
Integrated circuit with embedded identification code
An integrated circuit ( 100 ) has a plurality of inputs ( 110 ) and a plurality of outputs ( 120 ). In a test mode, a test arrangement including a plurality of logic gates ( 140 ) is coupled...
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7506226 |
System and method for more efficiently using error correction codes to facilitate memory device testing
A memory device includes an ECC and test circuit. In a normal mode, the circuit performs ECC conventional functions. In a test mode, the least significant bit of received data is used to generate...
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7502965 |
Computer chip set having on board wireless interfaces to support test operations
A method and apparatus are provided for an embedded wireless interface that is embedded in, for example, one of an input and output controller device for controlling input and output communications...
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7502724 |
Test simulator, test simulation program and recording medium
A test simulator for simulating a test of a semiconductor device is disclosed, the test simulator including: a test pattern holding unit for holding an existing test pattern to be supplied to the...
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7502974 |
Method and apparatus for determining which timing sets to pre-load into the pin electronics of a circuit test system, and for pre-loading or storing said timing sets
In one embodiment, a method includes, providing a test program designed to control a circuit test system. The circuit test system has a plurality of test channels, each test channel of which is...
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7500161 |
Correcting test system calibration and transforming device measurements when using multiple test fixtures
A test system and methods using the test system correlate measurements of a device under test (DUT) regardless of which test fixture is used for in-fixture testing of the DUT. The test system...
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7500164 |
Method for testing an integrated circuit device having elements with asynchronous clocks or dissimilar design methodologies
A method for testing an integrated circuit device with asynchronous clocks or dissimilar design methodologies is provided. With the method, each clock domain has its own scan paths that do not...
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7500147 |
Test system and method
A test system includes a terminal host and a to-be-tested circuit board. The terminal host generates a trigger signal. The to-be-tested circuit board includes a system chip, a memory and a...
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7496814 |
Load testing of a telecommunication network
A load testing apparatus and method has a display unit for the presentation of data that relate to a load test of a telecommunication network. The display includes a graphical user interface with...
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7495465 |
PVT variation detection and compensation circuit
A compensation circuit and a method that compensates for process, voltage and temperature (PVT) variations in an integrated circuit that includes functional modules. The compensation circuit...
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7496813 |
Communicating simultaneously a functional signal and a diagnostic signal for an integrated circuit using a shared pin
An integrated circuit 2 including functional circuits 4, 6 and a diagnostic circuit 10 passes a functional signal and a diagnostic signal to/from the integrated circuit using a shared...
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7496815 |
Method and apparatus for automatic generation of system test libraries
An apparatus and associated methodology are provided to generate system test libraries for solution testing involving heterogeneous devices from different vendors. A unified user interface employs...
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7496820 |
Method and apparatus for generating test vectors for an integrated circuit under test
Method, apparatus, and computer readable medium for generating test vectors for an integrated circuit (IC) under test is described. In one example, a test function is specified using at least one...
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7496490 |
Multi-core-model simulation method, multi-core model simulator, and computer product
Core model processing of a processor model PE1 and a processor model PE2 is serialized. Therefore, processing time for the inter-core-model communication is required between the core model...
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7493226 |
Method and construct for enabling programmable, integrated system margin testing
The present invention provides a margin testing system, incorporated in an electronic system (e.g., a computer system), that includes a controller, a frequency control module, and a voltage control...
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7493533 |
Delay detecting apparatus of delay element in semiconductor device and method thereof
A delay detecting apparatus detects delay amounts of delay elements in a semiconductor device by using a test mode. The semiconductor device comprises a delay signal detecting unit for detecting...
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7493535 |
JTAG circuit transferring data between devices on TCK terminals
The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK...
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7487571 |
Control adjustable device configurations to induce parameter variations to control parameter skews
A method is used for configuring an electronic device to reduce a skew of a parameter. The method includes a step of incorporating a plurality of controllable built-in parameter variation adjusting...
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7487415 |
Memory circuitry with data validation
Memory circuitry is augmented with data validation circuitry that is closely coupled to the memory circuitry so that data read out of the memory for use in a validation operation does not have to...
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7486725 |
Bit error rate tester and pseudo random bit sequences generator thereof
A bit error rate tester and a pseudo random bit sequences (PRBS) generator thereof are provided. The bit error rate tester includes a transmitter PRBS generator, a master PRBS generator, a slave...
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7487421 |
Emulation cache access for tag view reads
A built-in self test unit reads tag bits of a predetermined cache entry and outputs these tag bits via an external interface. The built-in self test unit enters an emulation mode upon receipt of an...
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7486997 |
Safety condition setting support device, program product and device control method for obtaining safety condition for safety network
A safety condition setting support device is used for a safety network to which an input device and an output device are connected and the output device serves to stop a controlled apparatus based...
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7487419 |
Reduced-pin-count-testing architectures for applying test patterns
Methods, apparatus, and systems for testing integrated circuits using one or more boundary scan cells are disclosed. The methods, apparatus, and systems can be used, for example, to apply at-speed...
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7487418 |
Semiconductor integrated circuit and method for testing same
An LSI which makes scan testing possible without compromising security is provided. Flip-flops that constitute a scan chain are reset when scan testing is initiated or terminated by the edges of a...
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7484141 |
Semiconductor device capable of performing test at actual operating frequency
A semiconductor device includes a CPU core circuit, a bus connected to the CPU core circuit, and a memory BIST circuit configured to perform a memory test in response to an instruction supplied...
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7484143 |
System and method for providing testing and failure analysis of integrated circuit memory devices
A system and method is disclosed for testing integrated circuits that contain memory devices. A plurality of test circuits is created in which each test circuit incorporates a physical fault in a...
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7484145 |
Method for embedded integrated end-to-end testing
A method and system for automated testing of a system such as a billing module in a telecommunication system is disclosed. In a first embodiment, test APIs, scenarios and configuration information...
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7484156 |
Apparatus and method for testing PS/2 interface
An apparatus for automatic testing of a PS/2 interface includes a micro controller unit, a PS/2 port, and a plurality of LEDs. The micro controller unit is coupled with both a data pin and a clock...
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7484146 |
Method for capturing multiple data packets in a data signal for analysis
A method for selectively capturing selected portions of multiple data packets within a packet data signal for analysis by capturing only desired or necessary portions of the data packets and...
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7484135 |
Semiconductor device having a mode of functional test
A semiconductor device includes a circuit block; a first signal path for guiding a test signal to a signal input terminal of the circuit block; a second signal path for guiding a test clock to a...
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7480839 |
Qualified anomaly detection
A circuit and method of qualified anomaly detection provides detection and triggering on specific analog anomalies and/or digital data within a qualified area of a serial data stream. A start...
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7480840 |
Apparatus, system, and method for facilitating port testing of a multi-port host adapter
An apparatus, system, and method are provided for facilitating port testing of a multi-port host adapter. The present invention includes a scheduler that schedules execution of a plurality of...
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7480602 |
System verification test using a behavior model
The present invention provides a system verification system that automatically generates a behavior model modeling the system under test in terms of actions of a test case and a range of expected...
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7480841 |
Semiconductor integrated circuit which properly executes an operational test of a circuit under test in the semiconductor integrated circuit
A semiconductor integrated circuit includes a circuit under test coupled to the logic circuit to receive a plurality internal test signals and a delay time measurement terminal from which a delay...
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7478302 |
Signal integrity self-test architecture
A method suitable for testing an integrated circuit device is disclosed, the device comprising at least one module, wherein the at least one module incorporates at least one associated module...
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7478295 |
Method and apparatus of fault diagnosis for integrated logic circuits
In a method for diagnosing faults in an integrated logic circuit including a plurality of input signal lines, a plurality of output signal lines and a plurality of gates connected between the input...
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7478300 |
Method for testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device
A method for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device is provided. With the method, each clock domain has its own scan paths that do not...
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7478304 |
Apparatus for accelerating through-the-pins LBIST simulation
The present invention provides an apparatus and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a...
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7478287 |
Semiconductor integrated circuit and electronic device
A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a...
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7478293 |
Method of securing the test mode of an integrated circuit via intrusion detection
An electronic circuit, including: a logic circuit having a plurality of logic cells; storage cells able to form a shift register, able to be connected to the logic cells; a connection control...
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