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7603603 |
Configurable memory architecture with built-in testing mechanism
A configurable memory architecture includes a built-in testing mechanism integrated in said memory to support very efficient built-in self-test in Random Access Memories (RAMs) with greatly reduced...
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7600167 |
Flip-flop, shift register, and scan test circuit
A flip-flop has a first latch and a second latch. The first latch has a first feedback circuit and a first selecting circuit which selects one of a first data input signal and an output signal of...
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7599826 |
System and method for generating various simulation conditions for simulation analysis
A system for generating various simulation conditions for simulation analysis is disclosed. The system includes: a signal generating module ( 301 ) for generating an N-bit binary sequence...
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7596731 |
Test time reduction algorithm
Exemplary embodiments provide a method and system for reducing test time for electronic devices. The method and system aspects include receiving a test data file containing results from a set of...
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7596730 |
Test method, test system and assist board
A test method for testing a device under test by using an event tester is provided. The test method includes: receiving a test signal generated by the event tester and applied to the device under...
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7596173 |
Test apparatus, clock generator and electronic device
There is provided a clock generator for generating a single-phase clock into which jitter has been injected, having a multi-phase clock generating section for generating a plurality of clock...
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7595467 |
Fault detection system and method for managing the same
A fault detection system comprises a data server configured to collect parameters incoming from at least one apparatus, at least one fault-sensing module configured to generate an alarm signal if...
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7596729 |
Memory device testing system and method using compressed fail data
A memory device testing system includes a signal generator providing memory command, address and write data signal to write data in a memory device and then read the data from the memory device....
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7594150 |
Fault-tolerant architecture of flip-flops for transient pulses and signal delays
A method and apparatus for a structure of a flip-flop that is tolerant to the noise pulses occurring due to the presence of crosstalk faults by sampling the input data multiple times before and...
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7590900 |
Flip flop circuit & same with scan function
A pulse-based flip flop, which outputs a scan input signal and a data signal, may include: a pulse generator to generate a pulse signal for coordinating operation of the flip flop; a multiplexer to...
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7590911 |
Apparatus and method for testing and debugging an integrated circuit
An integrated circuit includes a first deserializer that deserializes serial data containing at least one of test instructions and/or data in a first format. A monitor module communicates with the...
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7590901 |
Apparatus, system, and method for dynamic recovery and restoration from design defects in an integrated circuit
An apparatus, system, and method are disclosed for the recovery from a design defect in an integrated circuit. The apparatus includes an error check module, a control settings module, a retry...
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7590891 |
Debugging circuit and a method of controlling the debugging circuit
In a debugging circuit and a controlling method of the debugging circuit, a mode judgment signal is generated which indicates that a central processing unit (CPU) is preparing to debug a...
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7590904 |
Systems and methods for detecting a failure event in a field programmable gate array
An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA...
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7590903 |
Re-configurable architecture for automated test equipment
An adaptive test system includes one or more reconfigurable test boards, with each test board including at least one re-configurable test processor. The re-configurable test processors can transmit...
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7590902 |
Methods and apparatuses for external delay test of input-output circuits
Various methods and apparatuses are described for a system that includes some on-chip components, e.g., I-Os, test processors, soft wrappers, etc., an external testing unit that provides Parametric...
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7587642 |
System and method for performing concurrent mixed signal testing on a single processor
The present application describes a system and method for testing semiconductor devices and specifically for testing mixed signal semiconductor devices. The test systems are configured to test the...
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7587649 |
Testing of reconfigurable logic and interconnect sources
Methods and systems for verifying the proper function of reconfigurable logic elements and reconfigurable interconnects are disclosed. Reconfigurable logic elements in an emulation integrated...
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7584390 |
Method and system for alternating between programs for execution by cells of an integrated circuit
A method and device for data processing in an integrated circuit having cells, the cells adapted for executing programs. A first program is run. In response to a waiting condition during which no...
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7583604 |
Probe for measuring quality-of-service parameters in a telecommunication network
A measuring probe, able to access data flows composed of packets transmitted along a path formed by a plurality of equipment in a telecommunication network, having a measurement module to perform...
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7584392 |
Test compaction using linear-matrix driven scan chains
A scan technique using linear matrix to drive scan chains is used, along with an ATPG, to constraint scan test vectors to be generated through the linear matrix. The linear matrix scan technique...
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7581148 |
System, method and apparatus for completing the generation of test records after an abort event
A system for formatting test data includes at least one data formatter to retrieve test data from a data store, upon receiving notifications of test events, and to generate a number of test records...
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7577886 |
Method for testing an electronic circuit comprising a test mode secured by the use of a signature, and associated electronic circuit
An electronic circuit comprises a plurality of configurable cells configured according to a chaining command signal. These configurable cells are configured either in a chained state in which the...
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7577889 |
Method for detecting software errors and vulnerabilities
The present embodiments provide methods for detecting errors and vulnerabilities in software without access to its source code. The method entails extracting functions from dynamically linked...
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7574633 |
Test apparatus, adjustment method and recording medium
There is provided a test apparatus that tests a device under test including a plurality of data terminals and a clock output terminal, the test apparatus including a plurality of first variable...
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7574639 |
Method and apparatus for entering special mode in integrated circuit
A method and an apparatus for entering special mode in integrated circuit (IC) or logic circuit are provided. The IC or logic circuit receives a plurality of data bits and a reset signal, wherein...
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7574638 |
Semiconductor device tested using minimum pins and methods of testing the same
The present invention provides semiconductor devices capable of being tested using one test pin and using an input/output pin without any test pins, and methods of testing the same. One...
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7574634 |
Real time testing using on die termination (ODT) circuit
A system and method to operate an electronic device, such as a memory chip, in a test mode using the device's built-in ODT (on die termination) circuit is disclosed. One or more test mode related...
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7574637 |
Method and apparatus for optimized parallel testing and access of electronic circuits
A Parallel Test Architecture (PTA) is provided that facilitates concurrent test, debug or programmable configuration of multiple electronic circuits (i.e., simultaneously). The PTA includes a...
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7574644 |
Functional pattern logic diagnostic method
A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on functional failure by determining the...
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7571412 |
Method and system for semiconductor device characterization pattern generation and analysis
A method for generating automatic design characterization patterns for integrated circuits (IC) is provided. The method includes selecting a routing scheme from a file containing the device...
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7571363 |
Parametric measurement of high-speed I/O systems
A phase comparator is used to test a device under test comprising an input/output (I/O) circuit by applying a signal to the device under test; extracting a phase signal from the phase comparator;...
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7567883 |
Method and apparatus for synchronizing signals in a testing system
The preferred embodiments of the present invention provide approaches for synchronizing signals in a testing system. In some embodiments, the timing signal associated with each device under test...
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7568141 |
Method and apparatus for testing embedded cores
The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the...
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7565586 |
Method and apparatus for latent fault memory scrub in memory intensive computer hardware
A method for operating a memory checker in a command monitoring architecture comprising at least two processing lanes comprises a first step of receiving a command to activate a first test mode....
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7565582 |
Circuit for testing the AC timing of an external input/output terminal of a semiconductor integrated circuit
In a semiconductor integrated circuit, one of two signals generated from a first logic circuit is delayed in a first delay addition circuit, looped back by an input/output terminal, and then...
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7565589 |
Semiconductor integrated circuit having a BIST circuit
A semiconductor integrated circuit, includes a first external terminal which inputs a test signal, a second external terminal which external inputs a clock signal, a self-test circuit which...
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7565590 |
Logic circuit protected against transitory perturbations
The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit ( 10 ), having at least an output (A); a circuit ( 20 ) generating an error...
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7562275 |
Tri-level test mode terminal in limited terminal environment
A technique for increasing functionality of terminals of an integrated circuit without increasing the number of terminals of the integrated circuit utilizes at least one tri-level terminal and...
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7562271 |
Memory system topologies including a buffer device and an integrated circuit memory device
Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory...
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7562272 |
Apparatus and method for using eFuses to store PLL configuration data
An apparatus and method for using electrical fuses (eFuses) to store phase-locked loop (PLL) configuration data are provided. With the apparatus and method, a portion of the eFuses present in the...
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7562276 |
Apparatus and method for testing and debugging an integrated circuit
An integrated circuit (IC) comprises an embedded processor. An embedded in-circuit emulator (ICE) emulates at least one function of the embedded processor, performs at least one of testing and...
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7562170 |
Programmable extended compression mask for dynamic trace
This invention provides trace address compression by comparing respective bytes of a current trace address with a stored comparison address. Only the least significant bytes of the current trace...
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7559000 |
Integrated circuit device, diagnosis method and diagnosis circuit for the same
Hardware diagnosis of a disk array apparatus is conducted before shipment by using a self-diagnosis circuit, using the same criteria that apply to actual in-use equipment. A logical circuit and a...
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7558984 |
Apparatus and method for test and debug of a processor/core having advanced power management
An interface unit is provided in a JTAG test and debug procedure involving a plurality of processor cores. The interface unit includes a TAP unit. A switch unit is coupled to the interface unit and...
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7558995 |
Method and apparatus for eliminating noise induced errors during test of a programmable logic device
A method and apparatus for substantially eliminating noise induced errors caused by a premature start-up sequence between configuration of an integrated circuit (IC) and execution of functional...
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7558999 |
Learning based logic diagnosis
A system and method for diagnosing a failure in an electronic device. A disclosed system comprises: a defect table that associates previously studied features with known failures; and a fault...
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7558994 |
Methods and apparatus for data compression
A method and apparatus for compressing test vector data for use in testing a logic product, wherein original test vector data is generated in the form of two or more sequences of bits including...
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7555686 |
Semiconductor device, test board for testing the same, and test system and method for testing the same
Provided are a semiconductor device, a test board, and a test system and method for testing a semiconductor device. The semiconductor device includes an input terminal to which test pattern data is...
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7555689 |
Generating responses to patterns stimulating an electronic circuit with timing exception paths
Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit design having timing exception paths by more accurately determining the unknown values that...
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