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6823293 |
Hierarchical power supply noise monitoring device and system for very large scale integrated circuits
A hierarchical power supply noise monitoring device and system for very large scale integrated circuits. The noise-monitoring device is fabricated on-chip to measure the noise on the chip. The...
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6822474 |
On chip logic analyzer debug bus
A method, apparatus, and system for determining or observing internal state information in a chip.
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6816991 |
Built-in self-testing for double data rate input/output
Macro cells for a Double Data Rate (DDR) I/O interface are provided. The macro cells feature built-in self-test (BIST) functionality for testing the I/O interface at speed, without using external...
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6816989 |
Method and apparatus for efficiently managing bandwidth of a debug data output port or buffer
An output port for an integrated circuit includes a bandwidth manager for assisting in the off-loading of internal state data during debug periods. The bandwidth manager operates to take internal...
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6816821 |
Post image techniques
A device for synthesizing a reverse model of a system includes a first store storing bits representative of transition functions of the system, a second store storing bits representative of an...
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6816983 |
Microprocessor internally provided with test circuit
A microprocessor includes: a memory storing a program and various data; a processor core executing the program stored in the memory; an external bus interface serving as an interface portion of an...
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6813738 |
IC test cell with memory output connected to input multiplexer
A test cell ( 12 ) provides boundary scan testing in an integrated circuit ( 10 ). The test cell ( 12 ) comprises two memories, a flip-flop ( 24 ) and a latch ( 26 ), for storing test data. A first...
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6809545 |
Programmable power adjust for microelectronic devices
A circuit to adjust power is disclosed. The circuit comprises at least one pass gate and a power adjustor electrically coupled to each pass gate such that the power adjustor consumes power when the...
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6810497 |
Semiconductor integrated circuit compensating variations of delay time
A semiconductor device includes a first circuit and a second circuit cascaded therefrom, a pattern examination section for examining the input signal pattern for the first circuit to estimate a...
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6807646 |
System and method for time slicing deterministic patterns for reseeding in logic built-in self-test
A system and method for time slicing deterministic patterns for reseeding in logic built-in self-test (BIST). The known properties of a linear feedback shift register (LFSR) and an associated set...
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6804801 |
Integrated circuit fault insertion system
A system for fault insertion in an integrated circuit that resides in a functional portion of the integrated circuit. The fault insertion system is controlled through a Fault Control Register,...
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6801050 |
Driver circuit integrated with load current output circuit, pin electronics and IC tester having thereof
A driver circuit integrated with a load current output circuit has a function as a driver for applying a predetermined test waveform to a device under test (DUT), and a function as a load current...
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6799289 |
On-board testing circuit and method for improving testing of integrated circuits
A system allowing testing a plurality of integrated circuits mounted on a common substrate is described. The testing system includes a failure processor mounted on the substrate. The substrate has...
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6799130 |
Inspection method and its apparatus, inspection system
The present invention relates to a tool for analyzing by priority a defect having a high possibility of causing an electrical failure when inspecting a particle and a pattern defect in a piece of...
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6795788 |
Method and apparatus for discovery of operational boundaries for shmoo tests
Method and apparatus for discovery of operational boundaries for shmoo tests. Specifically, a method of testing operational boundaries is described in one embodiment of the present invention. The...
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6792386 |
Method and system for statistical comparison of a plurality of testers
The invention provides methods and systems for statistically comparing yields among two or more testers in a testing environment where a lot of manufactured articles such as semiconductor wafers...
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6779145 |
System and method for communicating with an integrated circuit
A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an...
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6771087 |
System and method for testing integrated circuit modules
Verification testing of modules packaged within an integrated circuit are conducted utilizing I/O ports of the integrated circuit for inputting or outputting incoming and outgoing signals, with...
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6772380 |
Smart tester and method for testing a bus connector
A system for testing a bus connector comprising an electronically controlled switch operatively coupled to be controlled by a microprocessor, the system having a first input operatively coupled to...
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6771061 |
High speed tester with narrow output pulses
A tester that is well suited for operation at high speeds or with narrow pulses. The tester includes a state based pulse shaping circuit that combines edge signals into a pulsed output signal. The...
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6769101 |
Systems and methods providing scan-based delay test generation
Chip analyzer systems and methods are provided to partition chip designs into smaller blocks in order to test speed paths more efficiently for integrated circuits. In accordance with one aspect of...
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6766485 |
Integrated circuit fault tester, integrated circuit fault test method and recording medium recorded with fault test control program
A unit test signal having duration T is repeatedly supplied from an LSI tester to an IC under test and, simultaneously, a power source current is supplied from the LSI tester through a current...
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6766486 |
Joint test action group (JTAG) tester, such as to test integrated circuits in parallel
A JTAG tester includes a JTAG controller in a PCI slot of a PC, a port multiplexer, a programmable power supply, and drive and compare logic, which tracks V cc . The tester reads and blows...
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6766484 |
Method and apparatus for fully characterizing propagation delay through an n-input circuit
One embodiment of the present invention provides a system that facilitates fully characterizing propagation delay through an n-input circuit. The system operates by first receiving the n-input...
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6762617 |
Semiconductor device having test mode entry circuit
A semiconductor device has a normal operation mode and a test mode. A decision circuit determines whether the device has entered the test mode. A control circuit changes information related to the...
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6763375 |
Method for defining and controlling the overall behavior of a network processor device
A system and method for controlling overall behavior of a network processor device implemented in a network processing environment servicing a communications network. The method includes steps of...
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6760873 |
Built-in self test for speed and timing margin for a source synchronous IO interface
A built-in self test implementation for testing the speed and timing margins of the IO pins of a source synchronous IO interface (SSIO). The implementation preferably includes built-in self test...
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6760874 |
Test access circuit and method of accessing embedded test controllers in integrated circuit modules
A test access circuit (TAC) for use in controlling test resources including child test access circuits (TACs) and/or test controllers, in an integrated circuit, comprises an enable input for...
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6760875 |
Method of testing a circuit using an output vector
A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. This circuit is driven by an additional output vector from the circuit. The additional...
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6757855 |
Integrated test apparatus and method therefor
An integrated apparatus and method for testing a very large scale integration (VLSI) device is implemented. An interface between automatic test equipment (ATE) and a device under test (DUT)...
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6757844 |
Architecture and logic to control a device without a JTAG port through a device with a JTAG port
An apparatus comprising a first circuit comprising a JTAG port and a second port. A JTAG non-compliant circuit may be controlled by the JTAG port when connected to the second port.
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6754861 |
Circuitry for and system and substrate with circuitry for aligning output signals in massively parallel testers and other electronic devices
Signal alignment circuitry aligns (i.e., deskews) test signals from a massively parallel tester. A timing portion of each signal is received by a rising edge delay element, a falling edge delay...
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6747468 |
Circuit trimming of packaged IC chip
To accomplish circuit trimming of a packaged IC chip by applying a magnetic field thereon, a magnetically configurable adjuster device is coupled with the packaged IC chip. The magnetically...
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6748563 |
Method and apparatus for testing path delays in a high-speed boundary scan implementation
A method and apparatus for testing path delays in a high-speed boundary scan implementation overcomes limitations imposed by pipelined high-speed clocking architectures used in integrated circuits....
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6745337 |
Glitch detection circuit for outputting a signal indicative of a glitch on a strobe signal and initializing an edge detection circuit in response to a control signal
A glitch detection circuit is described for detecting a glitch on a strobe signal transmitted over a single strobe interface. The glitch detection circuit includes a first input terminal to receive...
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6745370 |
Method for selecting an optimal level of redundancy in the design of memories
A method for determining the number of redundancy units to employ in a memory integrated circuit. The critical areas for faults on each process layer in the integrated circuit for a range of defect...
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6744274 |
Programmable logic core adapter
A programmable logic core (PLC) can be integrated into custom ICS such as ASICs and SOCs. An example PLC for integration into a custom IC includes a Multi Scale Array (MSA) that consists of an...
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6735543 |
Method and apparatus for testing, characterizing and tuning a chip interface
An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately...
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6735730 |
Integrated circuit with design for testability and method for designing the same
A test controller 4 has a test plan generating unit 11 for generating a test plan of a data path 2 which is formed to have a fixed control testability in which a test plan constituted by...
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6732310 |
Peripheral partitioning and tree decomposition for partial scan
A method, system and a computer product for a new partial scan technique that incurs significantly less overhead than the full-scan technique and yet achieves very high test coverage in short CPU...
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6732308 |
Integration of embedded and test mode timer
The present invention discloses an embedded and test mode timer circuit that is used to perform operations in an embedded mode and a plurality of test modes in a memory device. When the memory...
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6732307 |
Apparatus and method for storing trace information
A system for performing non-intrusive trace is provided which receives trace information from one or more processors. The trace system may be configured by a user to operate in various modes for...
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6728652 |
Method of testing electronic components and testing apparatus for electronic components
A method of judging whether an electronic component is good or defective in accordance with a response output signal by inputting a test signal to the IC to be tested, wherein a common test signal...
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6728916 |
Hierarchical built-in self-test for system-on-chip design
Hierarchical built-in self-test methods and arrangement for verifying system functionality. As a result, an effective built-in self-test methodology is provided for conducting complete...
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6728938 |
Knowledge-based intelligent full scan dump processing methodology
A systematic methodology to analyze a full scan dump is presented. The methodology is knowledge-based, i.e., the methodology intelligently processes a full scan dump using knowledge of the system...
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6725404 |
Evaluation of interconnect reliability using propagation delay through interconnect
An apparatus and method for reliability testing an electrical connector for an unacceptable propagation delay. The propagation delay is detected in a transmitted test signal through the electrical...
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6725405 |
Apparatus and method for providing a diagnostic problem determination methodology for complex systems
An apparatus and method for performing a diagnostic problem determination methodology for complex systems is provided. With the apparatus and method, a diagnostic application for a system may...
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6724212 |
Method for testing a semiconductor integrated circuit
In a method of testing a semiconductor integrated circuit, an input signal is applied to the semiconductor integrated circuit. Current passing through the elements of the semiconductor integrated...
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6725387 |
Method and apparatus for causing computer system interconnection to be in the same state each time test code is executed
A method and apparatus are disclosed for improving the repeatability of a system during testing by ensuring that the machine state remains the same on every test. In particular, the system ensures...
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6721912 |
Data carrier module having indication means for indicating the result of a test operation
A module ( 2 ) for a data carrier ( 1 ) includes an integrated circuit device ( 9 ) and transmission means ( 10 ), and the module ( 2 ) can be tested with the aid of test means ( 19 ) during a test...
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