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6918076 |
Method for providing bitwise constraints for test generation
A method for enabling bitwise or bit slice constraints to be provided as part of the test generation process, by providing a language structure which enables these constraints to be expressed in a...
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6918099 |
Method and system for entropy driven verification
A microelectronic device design verification system and method estimates the entropy of stimuli communicated over an interface to verify a microelectronic device design and feeds back the estimated...
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6914834 |
System and method for the functional testing of semiconductor memory chips
A system and a method for functionally testing fast semiconductor memory chips. The data shifting method proposed here is based on the fact that a low speed tester writes data and data strobe test...
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6915470 |
Data log acquisition circuit and data log acquisition method
In a data log acquisition circuit 100 , the number of executed test patterns counted by a number-of-patterns counter 1 , or the address of the test pattern is compared with a predetermined...
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6912678 |
System for identifying valid connections between electrical system components and responding to invalid connections
A method and circuitry for ensuring proper connections of a multi-wired cable bridging two electrical components in a programmable logic controller (PLC) system. The method involves: generating a...
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6910146 |
Method and apparatus for improving timing margin in an integrated circuit as determined from recorded pass/fail indications for relative phase settings
Under the control of a processor executing a program, the timing margin of an electronic system can be improved by a series of operations that set the relative phase of receive and distributed...
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6910164 |
High-resistance contact detection test mode
A method for testing a semiconductor memory device includes forcing the device into a logic state configuration that does not occur during normal operation of the device. The method may also...
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6903566 |
Semiconductor device tester
In a semiconductor device testing apparatus for testing a plurality of semiconductor devices at one time, data peculiar to each semiconductor device can be written therein simultaneously with the...
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6898746 |
Method of and apparatus for testing a serial differential/mixed signal device
Testing of a mixed signal electronic device, and evaluating of a test environment. A test driver applies an input test signal to the device. The response of the device is monitored on a...
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6897678 |
Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits
A programmable logic device is provided that contains circuitry that may be used for observing logic signals from programmable logic circuits on the device for testing the operation of the device....
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6898747 |
Method for testing circuit units to be tested with increased data compression for burn-in
The invention creates a method for testing circuit units ( 100 ) to be tested, in which test output signals ( 107 a -107 n ) can be combined, where test input signals ( 106 a -106 n ) are input...
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6898748 |
Test circuit method and apparatus
A test circuit for integrated circuit devices shortens test times, and reduces the length of the test pattern and the number of external terminals. The test circuit is provided between first and...
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6898563 |
System for aiding in the design of combinatorial logic and sequential state machines
A computer software tool for aiding in the design of combinatorial logic and sequential state machines comprising, according to the preferred embodiment, an apparatus and methods for representing...
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6898745 |
Integrated device with operativity testing
An integrated device having a pad receiving, in a standard operative condition, an input signal having a first value and, in a test operative condition, a test voltage having a second value higher...
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6893973 |
Method of etching silicon nitride film and method of producing semiconductor device
Provided is a method of etching a silicon nitride film, which comprises subjecting the silicon nitride film located on copper to dry etching using a mixture of fluorocarbon gas and an inert gas as...
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6895539 |
Universal method and apparatus for controlling a functional test system
An improved host controller application for controlling the testing of manufactured units such as circuit boards. The improved host controller uses a unique system and method for accessing and...
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6894503 |
Preconditional quiescent current testing of a semiconductor device
A method for testing a semiconductor device is included where sleep mode commands associated with the semiconductor device are generated. The semiconductor device includes logic blocks, where a...
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6895536 |
Testable up down counter for use in a logic analyzer
A logic analyzer according to the subject invention employs a bi-directional counter that can be incremented in response to detection of certain events, and decremented in response to detection of...
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6895548 |
Semiconductor testing apparatus and method for optimizing a wait time until stabilization of semiconductor device output signal
A semiconductor testing apparatus includes a test program memory for storing a test program, a measuring/deciding section for receiving the test program and supplying a test signal to the...
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6889348 |
Tester architecture construction data generating method, tester architecture constructing method and test circuit
The present invention provides a test circuit configuration technology suitable for use in a semiconductor device, which is capable of testing the semiconductor device without using a...
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6889334 |
Multimode system for calibrating a data strobe delay for a memory read operation
A system for coordinating the timing of a data strobe with data supplied by a memory module to the memory controller read data FIFO of a processor-based system, providing multiple calibration...
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6888366 |
Apparatus and method for testing a plurality of semiconductor chips
A semiconductor chip test system and test method thereof are provided. The system having a plurality of data input/output pins, a tester for inputting/outputting data through the plurality of data...
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6886122 |
Method for testing integrated circuits with memory element access
A method for testing an integrated circuit having memory elements which are written and/or read via an access path to the memory elements from a terminal external to the circuit. A boundary scan...
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6885952 |
System and method for determining voltage levels
A method for determining a power source voltage level of a power source in a system in which the power source is connected to a microcontroller. A charging circuit is in direct communication with a...
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6885961 |
Hybrid tester architecture
A hybrid tester architecture for testing a plurality of semiconductor devices in parallel is disclosed. The hybrid tester architecture includes per-pin formatting circuitry having data input...
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6885962 |
Signal inspection device
An inspection process and method that is performed not by the operation of a PC but within the inspection device itself according to the inspection program stored in a memory circuit in the...
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6882620 |
Token exchange system with fault protection
According to one embodiment, a system for controlling passing of a token among a plurality of clients that access a shared resource includes at least one controller. The at least one controller is...
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6883134 |
Method and program product for detecting bus conflict and floating bus conditions in circuit designs
A method and program product for verifying a logic design for proper operation of tri-state buses in the design, comprises, for each bus in the circuit design, determining the smallest cut set, a...
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6880116 |
System for testing multiple devices on a single system and method thereof
A system and method for testing multiple components using a single host system is shown and described. A host system with a single advanced graphics port (AGP) is used to generate commands of a...
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6876207 |
System and method for testing devices
A device testing system that has automated test equipment (ATE), which interfaces to a device under test (DUT). The device testing system selects a test set of data including a plurality of test...
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6871309 |
Verification of redundant safety functions on a monolithic integrated circuit
A method and apparatus for verifying that redundant circuits are truly redundant is provided. Extra circuitry is included within the integrated circuit to test the features of a chip. Without...
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6871310 |
Binary time-frame expansion of sequential systems
A processing system provides for analysis of sequential systems using binary time-frame expansion of these systems. This expansion technique produces models in which inputs and values for time may...
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6871308 |
Semiconductor inspection method
The present invention provides a semiconductor inspection method which detects a short circuit failure of adjacent lines having the possibility of a short circuit occurring, which short circuit...
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6868512 |
Fault detection system with real-time database
A method includes receiving incoming fault detection and correction (FDC) data. The incoming FDC data is stored in a real-time database, A first subscriber list designating a first subscriber for...
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6868532 |
Method and program product for designing hierarchical circuit for quiescent current testing and circuit produced thereby
A method of designing integrated circuits having an hierarchical structure for quiescent current testing, and the circuit which results therefrom is disclosed. The method comprises analyzing each...
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6864699 |
Apparatus for testing integrated circuits having an integrated unit for testing digital and analog signals
An apparatus for testing digital and analog signals from an integrated circuit includes an adder or subtractor 17 for being supplied with an analog signal outputted from the integrated circuit of...
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6865703 |
Scan test system for semiconductor device
There is provided a scan test system comprising: a semiconductor device including a scan register connected between an input/output pin on an analog input side and an internal system logic; a...
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6858447 |
Method for testing semiconductor chips
A method for testing semiconductor chips, in particular semiconductor memory chips, is described. In which, in a chip to be tested, at least one test mode is set, the test mode is executed in the...
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6857091 |
Method for operating a TAP controller and corresponding TAP controller
The present invention provides a method for operating a TAP controller having a first input terminal (Etms) for inputting a logic test mode selection signal (tms) and a second input terminal...
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6857089 |
Differential receiver architecture
A receiver circuit for a tester for electronic devices is provided. The receiver circuit includes a clock receiver that is adapted to receive a source synchronous clock signal from a device under...
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6857090 |
System and method for automatically analyzing and managing loss factors in test process of semiconductor integrated circuit devices
A system and method automatically analyzes and manages loss factor data of test processes in which a great number of IC devices are tested as a lot with a number of testers. The lot contains a...
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6851079 |
Jtag test access port controller used to control input/output pad functionality
A circuit that may be used to implement boundary scan testing. The circuit generally comprises a pad circuit, a core logic, a cell, and a test circuit. The pad circuit may be configured to transfer...
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6848049 |
Method and apparatus for the authentication of integrated circuits
A method for the authentication of an integrated circuit in an application system comprises, for the integrated circuit: detecting an activation scenario, and then modifying at least one of its...
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6848066 |
Error reduction in semiconductor processes
A photolithography system includes a photolithography tool 32 that includes a stage upon which a semiconductor wafer is mounted. The tool is operable to move the stage to automatically focus a...
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6845477 |
Semiconductor test device for conducting an operation test in parallel on many chips in a wafer test and semiconductor test method
A plurality of test target chips on a test target wafer are simultaneously and electrically coupled to a plurality of chips on a test wafer via a wafer contactor. Each chip on the test wafer has a...
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6845345 |
System for monitoring and analyzing diagnostic data of spin tracks
A system for analyzing diagnostic information associated with a spin track is provided. The system includes one or more analysis systems that collect diagnostic information from one or more spin...
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6839874 |
Method and apparatus for testing an embedded device
Method and apparatus for testing a device embedded in a programmable logic device is described. Because an embedded device, such as a microprocessor core, comprises more input and output pins than...
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6836757 |
Emulation system employing serial test port and alternative data transfer protocol
Emulation communications via a test access port and boundary-scan architecture providing serial access to a serial connection of a plurality of registers disposed in a plurality of modules. One of...
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6829553 |
Method of and apparatus for measuring the correctness of and correcting an automatic test arrangement
A method of and an apparatus for determining the correctness of the calibration of an automatic test arrangement and correcting errors in the automatic test arrangement. The electrical length is...
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6829730 |
Method of designing circuit having multiple test access ports, circuit produced thereby and method of using same
In a circuit with multiple Test Access Port (TAP) interfaces, the TAPs are arranged into groups, with secondary TAPs in one or more groups and a master TAP in another group, the master TAP having...
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