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6996759 |
Delay fault test circuitry and related method
The invention provides for a delay fault testing method and related circuitry for producing a test pulse in response to an input clock signal, and including analysing first and second clock signals...
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6993693 |
Analogue/digital interface circuit
An analogue/digital interface circuit is disclosed in which an integral bistable circuit has its state changed by the arrival of an incoming analogue signal, however transient, and irrespective of...
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6990614 |
Data storage apparatus and data measuring apparatus
A data storage apparatus comprising a scrambling circuit 34 for converting address signals and error data output by a tester 24 to a desired format, and a storage device 28 for storing the...
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6990621 |
Enabling at speed application of test patterns associated with a wide tester interface on a low pin count tester
According to some embodiments, at speed application of test patterns associated with a wide tester interface are enabled on a low pin count tester. For example, an integrated circuit might include...
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6990644 |
On chip timing adjustment in multi-channel fast data transfer
A method and structure for an apparatus for maintaining signal integrity between integrated circuits residing on a printed circuit board. The apparatus has adjustable delay circuitry within the...
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6987399 |
Systems and method for testing and recording temperatures of a CPU
A system for testing and recording temperatures of a central processing unit (CPU) includes a temperature detecting unit ( 11 ) for detecting a current temperature of the CPU at a test time; a...
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6986087 |
Method and apparatus for improving testability of I/O driver/receivers
An embodiment of this invention provides a circuit and method for improving the testability of I/O driver/receivers. First, two separate I/O driver/receiver pads are electrically connected. A bit...
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6986086 |
Method and device for simultaneous testing of a plurality of integrated circuits
An inventive device for simultaneous testing of a plurality of integrated circuits is described. Each integrated circuit of the plurality of integrated circuits includes a test mode, wherein a test...
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6986088 |
Method and apparatus for reducing the current consumption of an electronic circuit
The invention relates to a method for reducing the current consumption of an electronic circuit having at least one test module for testing the electronic circuit. The test module is connected to...
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6986085 |
Systems and methods for facilitating testing of pad drivers of integrated circuits
Integrated circuits (ICs) are provided. A representative IC includes a first pad electrically communicating with at least a portion of the IC. The first pad includes a first driver and a first...
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6983406 |
Method and system for partial-scan testing of integrated circuits
A method and system for partial scan testing of integrated circuits is disclosed. The invention includes determining at least one failed functional block during testing of the integrated circuit....
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6980943 |
Flow for vector capture
A method and system for generating a synchronous sequence of vectors from information originating within an asynchronous environment is disclosed. A simulated asynchronous sequence is synchronized...
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6981189 |
Interface circuit
There is disclosed an interface circuit capable of correcting the resistance value of a terminator according to a change in an ambient temperature or the like without causing any distortion in an...
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6981190 |
Controlling the content of specific desired memory elements when testing integrated circuits using sequential scanning techniques
A launch multiplexor which enables a desired bit to be stored into a desired memory element when using sequential scanning techniques (e.g., automatic test pattern generation (ATPG)). The launch...
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6978410 |
Test language conversion method
A method of converting test vectors in an original cycle based test language into a target cycle based test language, by forming a set of templates depicting waveforms defined in the target test...
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6977960 |
Self test circuit for evaluating a high-speed serial interface
A data transceiver including a self-test data generator for generating test data, which includes a first pseudo-random number generator programmable so as to allow the operator to input the test...
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6978231 |
Embedded hardware description language instrumentation
A method and program product for instrumenting a hardware description language (HDL) design entity. The design entity is created utilizing a HDL source code file within the syntax convention of a...
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6978409 |
Integrated circuit and testing method for integrated circuit
In testing of a plurality of logic circuits having the same function and included in an integrated circuit, an address decoder makes two logic circuits having the same function simultaneously...
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6975980 |
Hierarchical linking module connection to access ports of embedded cores
An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE Standard 1149.1. Access to and control of these ports is though a test linking module....
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6975954 |
Functional testing of logic circuits that use high-speed links
A method of testing a DUT is provided. The method comprises loading a memory within a link-based system with a functional test program, executing the functional test program in a processor core of...
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6973606 |
Partially distributed control mechanism for scanout incorporating flexible debug triggering
The invention includes an integrated circuit (IC). The IC includes an internal test bus (ITB). The IC also includes a number of deskew clusters connected to the ITB. The deskew clusters each...
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6973405 |
Programmable interactive verification agent
A verification agent can be used to verify hard and/or soft modules under test in an integrated circuit. The integrated circuit contains a processor and memory for storing code executable by the...
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6973607 |
Method and apparatus for testing electronic components
An apparatus and a method for testing one or more processors. The apparatus and method provide a host computer that issues test case information. The test case information is translated from the...
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6973609 |
Scan cell circuit and scan chain consisting of same for test purpose
A scan cell circuit for use in an integrated circuit chip is disclosed. The scan cell circuit includes a multiplexer receiving a first signal, a second signal and a selection signal, and outputting...
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6971052 |
Semiconductor integrated circuit and method for testing the same
When a test command is received n times, any one of a plurality of tests is started. After the first test is started, any one of the tests is started or terminated every time the test command is...
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6968485 |
Signal measurement apparatus and method
Ground bounce measurement circuitry, integrated circuit packaging, memory circuit modules, circuit cards, and systems, and methods to form, assemble, and use them are provided. A circuit...
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6966019 |
Instrument initiated communication for automatic test equipment
An automatic test system transfers measure data from one or more test instruments to a processor and processes the measure data, the packaging, transfer, and the processing of the measure data...
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6966018 |
Integrated circuit tester with multi-port testing functionality
Automated test equipment (ATE) includes a tester-per-pin architecture with a number of individual decentralized per-pin testing units, wherein each per-pin testing unit is adapted for testing a...
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6961690 |
Behaviorial digital simulation using hybrid control and data flow representations
The present invention provides a method and mechanism for simulating complex digital circuits using hybrid control and data flow representations. Specifically, the invention provides a method of...
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6961884 |
JTAG mirroring circuitry and methods
The present invention provides a JTAG mirroring circuit that augments the functionality of a JTAG circuit in an existing circuit design. The JTAG circuits include a TAP controller, an instruction...
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6961880 |
Recording test information to identify memory cell errors
A method of recording test information to identify a location of errors in Integrated Circuits (ICs) includes scanning a plurality of ICs with an input signal, each IC having a plurality of data...
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6957370 |
Digital signal processor including an interface therein capable of allowing direct access to registers from an external device
A DSP comprises pipeline registers, a logical operation circuit, a product-sum circuit, DSP registers and an interface. The DSP registers includes at least a plurality of program control registers...
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6956395 |
Tester for testing an electronic device using oscillator and frequency divider
A tester comprising a reference clock generating section for generating a reference clock having a first frequency, a first test rate generating section for generating a first test rate clock...
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6954716 |
Method of automatically resetting processing apparatus
According to the present invention, as processing apparatus drive starts, the operating state of software used to drive the processing apparatus is monitored in real time to diagnose whether or not...
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6950771 |
Correlation of electrical test data with physical defect data
Method and apparatus are disclosed for analyzing defect data produced in testing a semiconductor chip from a logic design. In various embodiments, input for processing is a first inspection data...
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6948105 |
Method of evaluating core based system-on-a-chip (SoC) and structure of SoC incorporating same
A method of debugging an individual core in core based system-on-a-chip (SOC) ICs with high accuracy and observability, and a structure of SOC incorporating the method. The method includes the...
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6944810 |
Method and apparatus for the testing of input/output drivers of a circuit
In order to test the input and output drivers of a circuit, in particular an integrated semiconductor circuit, a method and apparatus is provided to connect the input or output drivers assigned to...
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6944837 |
System and method for evaluating an integrated circuit design
A system and method for evaluating a device under test (DUT) that utilizes a model of the DUT interfaced to DUT interface logic, which is designed to interface the DUT to automated testing...
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6944809 |
Methods of resource optimization in programmable logic devices to reduce test time
Methods of optimizing the use of routing resources in programmable logic devices (PLDs) to minimize test time. A set of routing resources is identified that are not used in most designs, and a...
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6941496 |
Error detecting circuit for detecting the location of error
An error detecting circuit for detecting the location of an error is provided. The error detecting circuit has an error data storing unit and an error data collecting unit. The error data storing...
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6941497 |
N-squared algorithm for optimizing correlated events
An N 2 algorithm for optimizing correlated events, applicable to the optimization of the detection of redundant tests and inefficient tests (RIT's), is disclosed. This algorithm represents a set...
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6938191 |
Access control device and testing method
The present invention provides an access control device and a testing method that can simplify the software operations in an access control operation such as a JTAG control operation, and enable...
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6938194 |
Integrated circuit testing method and system
A system for testing an integrated circuit, the integrated circuit including: flip-flops connected to a logic block and the test system including circuitry for connecting the flip-flops as a...
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6934896 |
Time shift circuit for functional and AC parametric test
A time shift circuit for changing a delay timing of a portion of a test pattern for testing a semiconductor device. The time shift circuit includes a multiplexer for selectively producing delay...
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6931579 |
Integrated excitation/extraction system for test and measurement
An integrated test core for mixed-signal circuits comprises a periodic waveform generator capable of generating arbitrary band-limited waveforms for excitation purposes and a waveform digitizer for...
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6928596 |
Test circuit of semiconductor integrated circuit
A test code is input to a test mode control circuit so that the test mode control circuit creates the test decode signal. The test decode signal is converted into serial data with a...
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6928597 |
Method and apparatus for testing digital circuitry
Digital circuitry is tested through effecting a paired data loop-back from a first buffered output to a first buffered input whilst within the circuitry executing at least part of the test through...
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6925589 |
Method for translating physical cell-coordinates of a memory product to n-dimensional addresses
A structure and method for translating address buffer coordinates for a device under test having two or more similar repeatable units. The method comprises identifying a repeatable unit of the...
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6920597 |
Uniform testing of tristate nets in logic BIST
A built-in-self-test (BIST) circuit is discussed for selecting tristate nets with substantially uniform distribution using a tristate testing control device (TTCD). The circuit allows the...
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6918057 |
Architecture, circuitry and method for controlling a subsystem through a JTAG access port
Architecture, circuitry, and methods are provided for programming, writing to, or reading from one or more integrated circuits which may be arranged upon a printed circuit board. Programming and...
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