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7076705 |
Semiconductor integrated circuit having bonding optional function
Current consumption of an input unit with respect to a bonding option pad is reduced, and erroneous operation of a circuit connected to this bonding option pad is prevented. A boundary scan test...
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7073102 |
Reconfiguration device for faulty memory
A device for reconfiguring faults in a circuit comprised of several units and comprising storage means for storing the fault locations, connection/disconnection means for disconnecting faulty units...
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7073107 |
Adaptive defect based testing
A method of testing integrated circuits. Each of the integrated circuits is tested with a first test at a first level of testing at a preceding testing step in a fabrication cycle of the integrated...
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7073108 |
Communications jacks including test circuits and related circuits and methods
A jack for a communications line can include first and second input terminals configured to receive respective first and second conductors of a communications line, and first and second output...
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7073109 |
Method and system for graphical pin assignment and/or verification
A method, a system and/or a computer readable medium for accessing design data including an electronic image of an integrated circuit to be tested; determining whether a pin of the integrated...
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7069376 |
Flexibility of use of a data processing apparatus
A data processing apparatus and method of configuration of such an apparatus are provided, the apparatus comprising a plurality of logic elements for processing data, a plurality of storage...
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7062691 |
Method and apparatus for displaying test results and recording medium
There are provided a method and an apparatus for displaying test results and a recording medium, which allow easy detection of Devices for Testing in which probes are destroyed. The apparatus has...
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7062690 |
System for testing fast synchronous digital circuits, particularly semiconductor memory chips
A system and a method for testing fast synchronous digital circuit with an additional built outside self test semiconductor chip disposed between a test device and circuit under test. The chip has...
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7058865 |
Apparatus for testing semiconductor integrated circuit
An apparatus for testing a semiconductor integrated circuit has a test circuit board and an ancillary test device. The ancillary test device can test a digital circuit. The ancillary test device...
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7055060 |
On-die mechanism for high-reliability processor
A processor includes first and second execution cores that operate in a redundant (FRC) mode, an FRC check unit to compare results from the first and second execution cores, and an error check unit...
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7047462 |
Method and apparatus for providing JTAG functionality in a remote server management controller
The disclosed embodiments relate to the field of remote server management. More particularly, the embodiments relate to providing an embedded JTAG master in a remote server management controller....
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7047174 |
Method for producing test patterns for testing an integrated circuit
A test pattern generation flow has a stimulus and a device under test (DUT) that operate together through a test bench. The test bench monitors and collects all the data necessary to generate a...
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7047463 |
Method and system for automatically determining a testing order when executing a test flow
A method and system for automated multisite testing. Specifically, in one embodiment, a method is disclosed for determining a testing order of plurality of testing operations of a test flow in a...
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7043674 |
Systems and methods for facilitating testing of pads of integrated circuits
Methods for testing integrated circuits (ICs) are provided. An embodiment of a method comprises: electrically interconnecting automated test equipment (ATE) with the IC; providing at least one...
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7039840 |
Method and apparatus for high update rate integrated circuit boundary scan
Boundary scan cells for driving internal logic and sensing internal logic of integrated circuit use external clocks synchronized with internal functional clocks. Synchronized clocks enable...
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7039839 |
Method and apparatus for enhanced parallel port JTAG interface
A method and apparatus for an enhanced parallel port JTAG interface (IEEE Test Access Port) that includes a clock signal line where the clock signal line is a delayed and inverted version of a data...
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7039845 |
Method and apparatus for deriving a bounded set of path delay test patterns covering all transition faults
A method and apparatus for generating test patterns used to test an integrated circuit (IC). The apparatus comprises first logic for determining a subset of transition fault sites on an IC to be...
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7039838 |
Method for testing a circuit unit to be tested and test apparatus
The invention provides a method for testing a circuit unit ( 101 ) to be tested, in which a test time is reduced, at least one word line ( 102 a –102 N) of the circuit unit ( 101 ) to be tested...
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7039841 |
Tester system having multiple instruction memories
An apparatus for testing an integrated circuit includes a sequence control logic unit having an output channel connectable to an input pin of a device under test, a first memory to store a first...
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7036058 |
Semiconductor device having integrally sealed integrated circuit chips arranged for improved testing
Each chip includes, in addition to a core logic, a register such as a BSR. A TAPC for controlling the register is provided only on a chip of the first stage, and an test commands/data output and...
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7032145 |
System for dynamic re-allocation of test pattern data for parallel and serial test data patterns
A single memory automated test equipment (ATE) system having multiple pin segments with dynamic pin reallocation. Each pin segment having a length 2n is coupled to the single memory by a parallel...
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7032147 |
Boundary scan circuit
An electronic device includes a first circuit, a second circuit, and a boundary scan circuit. The boundary scan circuit includes a boundary scan register having a first cell connected to an input...
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7028237 |
Internal bus testing device and method
An internal bus testing device for a semiconductor integrated circuit in which an internal bus control circuit and a plurality of modules are linked by a plurality of internal buses. The internal...
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7024551 |
Method and apparatus for updating boot code using a system controller
Method and apparatus are disclosed that allow boot code within the apparatus to be updated using a system controller. The apparatus includes a central processing unit (CPU) and a programmable...
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7024328 |
Systems and methods for non-intrusive testing of signals between circuits
Structures and methods for non-intrusive testing of communication signals exchanged between two circuit boards via an intermediate interconnect board. In one aspect hereof, the functional signal...
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7024601 |
DVI link with circuit and method for test
An embodiment includes encoding digital data into encoded digital data in a transition minimized differential signaling encoder, serializing the encoded digital data into encoded and serial digital...
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7020571 |
Automated test method
An automated test method for performing a hi-pot test procedure for an electrical device through the use of a test program installed in a factory information system (FIS) and a test instrument...
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7020818 |
Method and apparatus for PVT controller for programmable on die termination
Embodiments include an on die termination circuit. The on die termination circuit may be programmable. The on die termination circuit may be programmed to compensate for environmental conditions...
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7020817 |
Method for testing semiconductor chips and semiconductor device
The delay characteristic of a chip under test on which a function test is performed first is detected by performing an edge search for stabilizing the test without awaiting the delay characteristic...
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7020813 |
On chip debugging method of microcontrollers
A microcontroller includes an external interface terminal group, a data transmit/receive section, and a DMA controller comprised of an address register for storing therein an address of a hardware...
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7020582 |
Methods and apparatus for laser marking of integrated circuit faults
Systems and methods are provided for marking integrated circuit defects on wafers to facilitate failure analysis. A wafer containing integrated circuits can be tested using a tester. Test data from...
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7020573 |
Enhanced testing for compliance with universal plug and play protocols
The present invention extends to methods, systems, and computer program products for enhanced Universal Plug and Play (“UPnP™”) compliance testing. A control point (e.g., a computer system)...
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7017092 |
On-chip design for monitor
A monitoring device on-chip. The monitoring device includes characteristic circuits, test circuits, and select circuits and is incorporated into an integrated circuit. The test circuit is cascaded...
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7017093 |
Circuit and/or method for automated use of unallocated resources for a trace buffer application
An apparatus including a first circuit, a second circuit, and a third circuit. The first circuit may be configured to receive a plurality of input signals and present one of the plurality of input...
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7017091 |
Test system formatters configurable for multiple data rates
A test system formatter may include a programmable drive circuit configurable to operate in any of a plurality of drive modes, each mode corresponding to a different combination of drive signals or...
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7017094 |
Performance built-in self test system for a device and a method of use
A semiconductor device is disclosed that include a built-in self test system. The device comprises a logic function and a self test engine coupled and integrated with the logic device. The device...
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7010722 |
Embedded symmetric multiprocessor system debug
A test signal multiplexer receives supplies external test signals to a selected debug master central processing unit in a symmetrical multiprocessor system and debug slave signals to debug slave...
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7010452 |
Event pipeline and summing method and apparatus for event based test system
An event pipeline and vernier summing apparatus for high speed event based test system processes the event data to generate drive events and strobe events with various timings at high speed to...
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7010734 |
Method for microprocessor test insertion reduction
Methods for reducing the requirement for multiple test vector sub-set insertions of a test vector set on test equipment having a limited memory size. In one embodiment, a single, selective test...
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7010733 |
Parametric testing for high pin count ASIC
A method for reducing Pin Count Test design and test that allows parametric test patterns for high pin count ASICs to be applied using low pin count testers. The same boundary scan structure used...
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7007215 |
Test circuit capable of testing embedded memory with reliability
A test signal applied to an embedded memory is changed in synchronization with a test clock signal, set to an invalidated state by an asynchronous control signal asynchronous to the test clock...
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7007212 |
Transmission device, reception device, test circuit, and test method
The present invention provides a transmission device, a reception device, a test circuit and a test method, which enable internal parts of the circuit to operate at high speed, while performing...
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7002365 |
Method and an apparatus for testing transmitter and receiver
A method and an apparatus for testing transmitter and receiver have been disclosed. One embodiment of the apparatus includes a plurality of multiplexers to select one of a positive transmitter pin...
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7003707 |
IC tap/scan test port access with tap lock circuitry
Connection circuitry provides for TAP and internal scan test ports to be merged so they both can co-exist and operate from the same set of IC pins and/or core leads or terminals. This arrangement...
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6998837 |
Serial communication testing
A coupling unit provides a signal path between at least two of: a first device under test (DUT), and first and second couplers. The first coupler is coupled to a signal analyzer. The second coupler...
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6998866 |
Circuit and method for monitoring defects
A circuit and a method for monitoring defects in an integrated circuit chip. The circuit including a defect monitor portion and a sense element portion, the defect monitor portion either coupled to...
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6996754 |
Integrated circuit device having an internal state monitoring function
An integrated circuit device for testing is disclosed. The device includes a plurality of internal circuits for generating a plurality of internal signals, the internal signals used for addressing...
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6996760 |
ASIC BIST employing stored indications of completion
A method and apparatus for performing a built-in self-test (“BIST”) on an integrated circuit device are disclosed. A BIST controller comprises a BIST engine and a register. The BIST engine is...
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6996757 |
Test system rider board utilized for automated at-speed testing of high serial pin count multiple gigabit per second devices
A test head performs at-speed testing of high serial pin count gigabit per second (GBPS) devices. The test head includes a device under test (DUT) coupled to a first portion of the test head and a...
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6996755 |
Squence control circuit
A sequence control circuit that is capable of operating at high-speed without using either a memory having a short access time or high-speed devices is provided. Each address of an instruction...
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