Matches 1 - 50 out of 72 1 2 >
Match Document Document Title
7613982 Data processing apparatus and method for flash memory  
A data processing apparatus and method for a flash memory, which make it easy to determine whether data stored in the flash memory is valid, are provided. The data processing apparatus includes a...
7600161 Method of verifying integrity of control module arithmetic logic unit (ALU)  
A method of verifying the integrity of an arithmetic logic unit (ALU) of a control module includes inputting a first test value into one of a plurality of registers of the ALU and inputting a...
7558993 Test apparatus for semiconductor memory device  
A test apparatus for a semiconductor memory device applies a test input pattern to the semiconductor memory device to produce a test output pattern. The test apparatus compares the test output...
7533249 Reconfigurable integrated circuit, circuit reconfiguration method and circuit reconfiguration apparatus  
In order to reuse configuration information in a dynamic reconfiguration arithmetic circuit, data lines, address lines, a mask register and the like are required as hardware resources for rewriting...
7496965 Data recording medium, data recording method, data processing device, data distribution method, data distribution device, data transmission method, data transmission device, data distribution system, and data communication system  
On a CD-R, a UID that is unique identification information is pre-recorded. When the CD-R is loaded into an information terminal unit, the UID is read and transmitted to a management server through...
7461308 Method for testing semiconductor chips by means of bit masks  
A method for testing semiconductor chips is disclosed. In one embodiment, a chip to be tested which has a test logic, at least one test mode is set, the test modes are executed in the chip and test...
7454676 Method for testing semiconductor chips using register sets  
A method for testing semiconductor chips having a test logic unit includes: providing a chip having n different register sets, each of which has m different registers that are subdivided into m...
7386769 On chip diagnosis block with mixed redundancy  
On chip diagnosis method and on chip diagnosis block with mixed redundancy (IO redundancy and word-register redundancy) is provided. During a BIST (Built-In Self Test), information needed to apply...
7366597 Validating control system software variables  
A vehicle having a system for validating a variable signal for input to a processor-performed function. An input module receives the signal. A processor tests first and second storage locations of...
7353400 Secure program execution depending on predictable error correction  
A CPU is provided with an ability to modify its operation, with respect to error correction, as a programmable feature. An error correction scheme is selected to be performed by the error...
7296197 Metadata-facilitated software testing  
Described herein are one or more implementations for facilitation of computer software testing. One or more implementations, described herein, determine logical type of one or more test...
7287204 Memory unit test  
The invention relates to a method and device for operating and/or testing memory units, which make it possible to conduct a time-saving test of semiconductor memories during running operation. The...
7203580 Electrical control unit and control system comprising plural electrical control units  
When ENG frames created in an ENG transceiver unit and ECT frames subjected to gateway processing in an ECT gateway processor are transmitted around the same time, a transmission mediating unit...
7136316 Method and apparatus for data compression in memory devices  
A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of complementary digit lines is provided for each...
7127650 Test method and test device for electronic memories  
A test method for electronic memories includes reading out a previously defined test pattern sequentially as a time-dependent signal from the memory, determining the associated spectrum from the...
7111210 Accelerated test method for ferroelectric memory device  
An accelerated test method evaluates, under accelerated conditions (a temperature T 2 and a voltage V 2 ), an endurance characteristic of a ferroelectric memory device having a capacitor element...
6971053 Method for initiating internal parity operations in a CAM device  
A circuit and a method of operating the circuit is provided. The method generally comprises the steps of (A) receiving an explicit error checking instruction generated outside the circuit, (B)...
6799291 Method and system for detecting a hard failure in a memory array  
A method and system for detecting a failure in a dynamic random access memory (DRAM) array having a plurality of cells organized in a matrix fashion of rows and columns. The method includes reading...
6754859 Computer processor read/alter/rewrite optimization cache invalidate signals  
A plurality of processors in a data processing system share a common memory through which they communicate and share resources. When sharing resources, one processor needs to wait for another...
6732306 Special programming mode with hashing  
A method wherein a special programming mode of a memory is entered. The special programming mode disables internal verification by the memory. The memory includes automation circuitry for program...
6633999 Integrated circuit with on-chip data checking resources  
An integrated circuit with on-chip resources to support the testing of data stored on the integrated circuit includes logic to compute a check code using data, or a combination of data and...
6553521 Method for efficient analysis semiconductor failures  
The present invention includes a method for characterizing semiconductor failure. The method includes determining the dimensions of certain characteristics of a memory chip. The method defines a...
6519694 System for handling load errors having symbolic entity generator to generate symbolic entity and ALU to propagate the symbolic entity  
In a RISC or CISC processor supporting the IEEE 754 Not-a-Number (NaN) standard and of the kind comprising a load/store unit, a register unit and an arithmetic logic unit, and wherein the...
6510527 Method and system for data protection  
A method and a system for data protection of fixed and learned control data of duplicated, program-controlled computers, in which the control parameters are stored in an EEPROM. The memory...
6467056 Semiconductor integrated circuit and method of checking memory  
A test circuit comprised of a microprogram controlled control unit for generating a test pattern (addresses and data) for each memory in accordance with a predetermined algorithm and reading...
6317372 Semiconductor memory device equipped with serial/parallel conversion circuitry for testing memory cells  
An input conversion unit converts serial data supplied from the exterior into parallel data. Each of the converted parallel data is respectively written into a plurality of memory cell areas. An...
6226766 Method and apparatus for built-in self-test of smart memories  
A self-testing smart memory (28) is provided in which memory test circuitry (46) within the smart memory (28) writes a pattern to a data RAM (32) and a broadcast RAM (34) and then reads the data...
6202187 Pattern generator for use in a semiconductor test device  
A pattern generator for use in a semiconductor test device provided with a random access memory which has large capacity and runs at high speed and is capable of generating random pattern data...
6148425 Bist architecture for detecting path-delay faults in a sequential circuit  
A scan-based BIST architecture for detecting path-delay faults in a sequential circuit converted to a combinational circuit or a less complex sequential circuit including a combinational portion...
6141781 Process for editing of data, in particular with variable channel bit rate  
For processing data, particularly for transmission via a channel with an specifiably variable data rate, the data are classified into bit classes that are provided with different error redundancy....
6081912 Method for modulating data for storage in page-wise memory  
Embodiments of the invention include a method and apparatus for modulating data retrieved from page-wise memory systems such as holographic memory systems. The inventive method uses the detection...
5928370 Method and apparatus for verifying erasure of memory blocks within a non-volatile memory structure  
In a digital system having non-volatile memory devices for storage of digital information therein, the digital information being organized in sectors, each sector having a data field and a...
5822786 Apparatus and method for determining if an operand lies within an expand up or expand down segment  
Dedicated parallel comparators perform expand up or expand down segment limit checks for memory accesses. A first three-input comparator has as inputs the complement of the segment limit, the...
5740178 Software for controlling a reliable backup memory  
An Electrically Erasable Programmable Read Only Memory (EEPROM) provides backup and initialization data for random access memory (RAM) in a control unit. In order to update the EEPROM with new...
5717697 Test circuits and methods for integrated circuit having memory and non-memory circuits by accumulating bits of a particular logic state  
An integrated circuit including a semiconductor chip and chip circuitry including memory circuitry and additional non-memory circuitry all fabricated on the semiconductor chip. The chip circuitry...
5654588 Apparatus for performing wafer-level testing of integrated circuits where the wafer uses a segmented conductive top-layer bus structure  
Wafer level testing of a wafer (500) is accomplished by dividing the integrated circuits of the wafer into a plurality of segmented bus regions (514, 516, and 518 for example). Each bus region is...
5652580 Method and apparatus for detecting duplicate entries in a look-up table  
A method and apparatus detects whether more than one object has been selected from a set of objects. A unique code and an error code is coupled to objects in the set. At least one object is...
5644704 Method and apparatus for verifying the contents of a storage device  
A method and apparatus for verifying the contents of a storage device. A number of steps are involved in performing the verification. First, non-sequential data is written into each unused memory...
5629946 High speed test pattern generator  
A test pattern generator which is capable of generating a test pattern with high speed without requiring complicated programming is disclosed. The test pattern generator includes a parallel circuit...
5590134 Test circuits and method for integrated circuit having memory and non-memory circuits by accumulating bits of a particular logic state  
An integrated circuit includes read/write memory and non-memory circuitry. A detector generates a count of the number of bits of each data words recalled from the memory having a predetermined...
5517506 Method and data processing system for testing circuits using boolean differences  
A test vector generator system (157) and method for generating test vectors for testing integrated circuit speed paths involves accessing both a circuit model (160) and a list of circuit paths...
5497350 Integrated semiconductor memory device capable of switching from a memory mode to an internal test mode  
A semiconductor memory is subdivided into a plurality of function units and has m leads addressable from outside, internal signal lines leading from the function units to the leads, internal signal...
5469444 Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels  
An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit...
5467357 EEPROM apparatus  
An EEPROM apparatus being provided with, in an ECC circuit (6), an ECC code generating unit (19) which automatically generates "5(H)" ((H) represents hexadecimal number), that is, "0101(B)" ((B)...
5442641 Fast data compression circuit for semiconductor memory chips including an array built-in self-test structure  
A fast high-density data compression circuit adapted to semiconductor integrated circuits of the memory type including an ABIST unit. This circuit, which compares the data-out signals output by the...
5404495 Microcomputer having an error-correcting function based on a detected parity error  
A microcomputer having an error correction function includes a summing function for calculating a total-sum of data associated with a block of stored data, a total-sum changing function for...
5349697 Radiotelephone including battery-backup random access memory for storing operating code  
The program code of an object program of a radiotelephone is recorded into a RAM (3) rather than in an EPROM as is conventional. The checking of the program code and the loading of the program from...
5321706 Method and apparatus for checking the address and contents of a memory array  
A circuit for checking the memory array address and contents is described. The circuit consists of at least one write address counter (120) and at least one read address counter (130). Before a...
5271015 Self-diagnostic system for semiconductor memory  
A self-diagnostic memory checking system includes a data generator for generating and applying data to a selected address of a memory when a CPU is in a memory write mode and generating expected...
5181206 PROM writer having check sum function  
The present invention relates to a PROM writer which functions to compare the first check sum value of the first or reference data read out a master ROM with the check sum values of the second and...
Matches 1 - 50 out of 72 1 2 >