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7386650 Memory test circuit with data expander  
A memory test circuit receives test pattern data from a processing unit having a first data width, expands the test pattern to a second data width greater than the first data width, and writes the...
7376889 Memory device capable of detecting its failure  
A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for...
7353438 Transparent error correcting memory  
A memory system with transparent error correction circuitry provides full stuck-at fault coverage for both test data patterns and the corresponding error correction code (ECC) values. The memory...
7346817 Method and apparatus for generating and detecting initialization patterns for high speed DRAM systems  
A method and apparatus for determining the characteristics of a communications channel within a high speed memory system includes generating a first signal having a known and repeating pattern and...
7325176 System and method for accelerated information handling system memory testing  
Memory testing at system startup, such as boot POST, of an information handling system is accelerated by adjusting memory testing routines to use instructions that take advantage of optimizations...
7324392 ROM-based memory testing  
This invention uniquely partitions the pBIST ROM for storing program and data information. The pBIST unit selectively loads both the algorithm and data, the algorithm only or the data only for each...
7324391 Method for determining and classifying SRAM bit fail modes suitable for production test implementation and real time feedback  
A method ( 200 ) for determining various bit failure modes in a static random access memory device. A hard/soft bit failure test sequence is performed on each cell of the memory device to determine...
7319623 Method for isolating a failure site in a wordline in a memory array  
According to one exemplary embodiment, a method for isolating a failure site in a leaky wordline in a memory array includes dividing said leaky wordline into an initial leaky wordline portion and...
7294998 Timing generation circuit and semiconductor test device having the timing generation circuit  
A timing generation circuit can increase a maximum delay amount without changing the configuration of a timing memory. The timing generation circuit includes: a timing memory (TMM) 10 containing...
7275188 Method and apparatus for burn-in of semiconductor devices  
A method and apparatus for burn-in of semiconductor devices is disclosed. A semiconductor device that includes built-in self test circuitry is coupled to a socket on a burn-in board. The burn in...
7269766 Method and apparatus for memory self testing  
A self-test controller 10 is responsive to scanned in self-test instructions to carry out test operations including generating a sequence of memory addresses that is specified by the self-test...
7257754 Semiconductor memory device and test pattern data generating method using the same  
A semiconductor memory device includes a mode setting register for generating a parallel bit test signal and a code according to an externally applied mode setting register code in response to a...
7248516 Data compression read mode for memory testing  
Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data...
7237157 Procedure and device for identifying an operating mode of a controlled device  
A procedure is provided for identifying an operating mode of a device, such as an EEPROM memory that communicates according to a communication protocol, such as “I 2 C” (Inter Integrated...
7225372 Testing board for semiconductor memory, method of testing semiconductor memory and method of manufacturing semiconductor memory  
A testing circuit using ALPG is mounted in a testing board in which sockets for mounting semiconductor memories as devices to be tested in the board is mounted and a volatile memory for storing a...
7222273 Apparatus and method for testing semiconductor memory devices, capable of selectively changing frequencies of test pattern signals  
There are provided an apparatus and method for testing semiconductor memory devices, in which the frequencies of test pattern signals can be selectively changed. The test apparatus includes a main...
7219276 Testing CMOS CAM with redundancy  
A method for testing an CMOS ternary content addressable memory (TCAM) device includes a match line test to identify stuck match lines, a pull down test to identify weak pull downs (from the match...
7197673 Memory interlace-checking method  
The present invention relates to a memory interlace-checking method and, in particular, to a test method that can effectively detect the weakening of memory. This test method is different from the...
7180803 Data compression read mode for memory testing  
Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data...
7178076 Architecture of an efficient at-speed programmable memory built-in self test  
A method of testing an embedded memory at speed within an integrated circuit which includes providing a memory built in self test sequencer module, providing a satellite engine module coupled to...
7139946 Method and test circuit for testing memory internal write enable  
A method of testing write enable lines of random access memory having at least one word having one or more write enable inputs for controlling write operations in the word, comprises, for a...
7117409 Multi-port memory testing method utilizing a sequence folding scheme for testing time reduction  
In a method of testing a multi-port memory in accordance with a test pattern, test clock signals having the same test clock frequency but with different delay periods introduced therein are...
7117408 Method and system of testing data retention of memory  
A method and system of testing data retention of memory is provided. An embodiment of the method of testing data retention of memory comprises: writing first data to a first memory sub-group during...
7113435 Data compression read mode for memory testing  
Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data...
7096394 Method for protecting software programs from inadvertent execution  
A method of safeguarding program parts which are critical to safety against inadvertent execution is described. In this method, at least one program part is executed in a predetermined...
7085975 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data...
7073106 Test method for guaranteeing full stuck-at-fault coverage of a memory array  
A method, computer program product and system for testing stuck-at-faults. A first register may be loaded with a first value where the first value may be written into each entry in a memory array....
7065689 Diagonal testing method for flash memories  
The present invention discloses a diagonal testing method for flash memories. The testing method regards the flash memory as several squares, and executes in the direction from top to bottom and...
7062686 Data copy protection using reproduction error determination and predetermined pattern recognition  
When a program is activated, data recorded in a predetermined sector is reproduced by an error correction. When no reproduction error occurs, the data in the predetermined sector is reproduced...
7035752 Semiconductor test data analysis system  
A semiconductor test data analysis system ( 1 ) automatically recording, during an analysis operation, operation information of the analysis operation, including analysis conditions or an analysis...
7031868 Method and apparatus for performing testing of interconnections  
The present invention provides a method and apparatus configured to allow testing of interconnections between components in a system. The present invention utilizes a source of a known pattern, for...
7024604 Process for manufacturing semiconductor device  
A semiconductor device manufacturing process which includes a test process that minimizes the test time for a single wafer, reduces the test cost and improves the throughput. The test system is...
7024603 Arrangement for verifying that memory external to a network switch and the memory interface are free of defects  
A method and arrangement is provided for testing memory external to a network switch and a memory interface bus connecting the external memory to the network switch. The method includes writing,...
7007210 Method and system for handling multiple bit errors to enhance system reliability  
The present invention provides an improved method, an system, and a set of computer implemented instructions for handling a cache containing multiple single-bit hard errors on multiple addresses...
6964000 Semiconductor integrated circuit device having a test circuit of a random access memory  
32 pseudo-random numbers respectively indicated by 5 bits are successively generated in a test address generating unit, a serial output signal denoting one pair of pseudo-random numbers of 10 bits...
6938193 ECC circuit-containing semiconductor memory device and method of testing the same  
In an ECC circuit of an ECC circuit-containing semiconductor memory device, an error correcting code/syndrome generating circuit and a data correcting circuit are disposed. In portions of the ECC...
6918075 Pattern generator for semiconductor test system  
A pattern generator for semiconductor test system for testing a semiconductor memory device by generating and applying test patterns. The pattern generator is capable of freely generating inversion...
6854080 Memory LSI failure analysis apparatus and analysis method thereof  
Provided are a device, method and storage medium, which, when a memory LSI defect analysis apparatus is used as a monitoring device to estimate reductions in yield, automatically interprets...
6842866 Method and system for analyzing bitmap test data  
A system for analyzing bitmap test data includes a fault shape analyzer which continuously and automatically receives bitmap test data. In use, the user creates at least one failure pattern...
6826720 Testing board for semiconductor memory, method of testing semiconductor memory and method of manufacturing semiconductor memory  
A testing circuit using ALPG is mounted in a testing board in which sockets for mounting semiconductor memories as devices to be tested in the board is mounted and a volatile memory for storing a...
6760857 System having both externally and internally generated clock signals being asserted on the same clock pin in normal and test modes of operation respectively  
A clock signal driven device has a clock pin for receiving an externally generated clock signal during normal operation. Internal circuitry coupled to the clock pin is responsive to the externally...
6754858 SDRAM address error detection method and apparatus  
Synchronous dynamic random access memory (SDRAM) method and apparatus are provided for implementing address error detection. Addressing errors are detected on the memory interface independent of...
6728652 Method of testing electronic components and testing apparatus for electronic components  
A method of judging whether an electronic component is good or defective in accordance with a response output signal by inputting a test signal to the IC to be tested, wherein a common test signal...
6704677 Method and apparatus for generating a data pattern for simultaneously testing multiple bus widths  
One embodiment of the present invention provides a system that facilitates generating a bus testing data pattern for simultaneously testing multiple bus widths. The system first receives a list of...
6701472 Methods for tracing faults in memory components  
There are disclosed methods and apparatus for testing memory components for faults, defects or the like, by generating a testing sequence that produces various bit combinations as well as current...
6701470 Method for testing a memory device having different number of data pads than the tester  
Testing a memory device having M data pads with a tester having N<M data pads, comprising writing data to the memory device in a test configuration; then in a normal configuration reading the...
6687766 Method and apparatus for a fibre channel control unit to execute search commands locally  
The present invention provides a method for fibre channel control units to execute commands locally when a channel sends a repeat execute indicator in conjunction with certain other field settings,...
6647523 Method for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the applied data signals were properly captured. A first group of the...
6647522 Semiconductor devices having multiple memories  
A semiconductor device having multiple memory circuits of varying sizes includes scan test circuitry that enables the memories to be simultaneous loaded with pattern data and tested. A first memory...
6647521 Memory testing method and apparatus, and computer-readable recording medium  
A memory testing method tests a memory by writing test data to and reading test data from the memory. Data is successively read from the memory is synchronism with a clock and the data is compared....
Matches 1 - 50 out of 203 1 2 3 4 5 >