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6647522 Semiconductor devices having multiple memories  
A semiconductor device having multiple memory circuits of varying sizes includes scan test circuitry that enables the memories to be simultaneous loaded with pattern data and tested. A first memory...
6647521 Memory testing method and apparatus, and computer-readable recording medium  
A memory testing method tests a memory by writing test data to and reading test data from the memory. Data is successively read from the memory is synchronism with a clock and the data is compared....
6640321 Built-in self-repair of semiconductor memory with redundant row testing using background pattern  
A method is presented for self-test and self-repair of a semiconductor memory device. Prior to the self-repair stage, both redundant and regular memory portions are comprehensively tested,...
6629275 Reinstate apparatus and method to recreate data background for testing SRAM  
A system for recreating a data background to test memory designs for macros includes a macro, a first multiplexer, and a second multiplexer. The macro includes a plurality of flip-flops. The first...
6601205 Method to descramble the data mapping in memory circuits  
An automatic method for the generation of a logical hardware test pattern in memory circuits is based on a given physical pattern. The method includes backwards transformation from a given set of...
6587979 Partitionable embedded circuit test system for integrated circuit  
A flexible built-in self-test (BIST) circuit is incorporated into an integrated circuit (IC) for testing one or random access memories or other memories embedded in an integrated circuit regardless...
6571364 Semiconductor integrated circuit device with fault analysis function  
A semiconductor integrated circuit device with fault analysis function performs test operation for a memory circuit (such as a RAM) in which a comparison control circuit ( 6 ) generates a...
6567940 Method of testing random-access memory  
A method of testing RAM without destroying the stored data consists of looping through the locations to be tested ( 21, 28, 29 ), and at each location, inverting the data stored in the location (...
6550027 Method and article of manufacture for differentiating between a non-volatile memory device and an emulator for purposes of in-circuit programming  
The present invention relates to a method and an article of manufacture for differentiating between an in-circuit programming read-only memory (“ROM”) and a ROM emulator for purposes of...
6539324 Semiconductor device and semiconductor device testing method  
It is one object of the present invention to eliminate redundant testing steps from an operation for testing the search function of a content addressable memory having a priority encoder. Before...
6523135 Built-in self-test circuit for a memory device  
A built-in self-test (BIST) circuit in a DRAM has a test mode controller including a mode counter for selecting based on the count thereof one of a plurality of test modes, and a plurality of test...
6513138 Pattern generator for semiconductor test system  
A pattern generator for generating a test pattern that has a repetition rate higher than the basic repetition rate thereof to test a synchronous memory. The test pattern to be provided to a memory...
6490700 Memory device testing apparatus and data selection circuit  
A memory device testing apparatus has a pattern generator, which generates all of the signals used for a packet signal in one cycle, a pin data selector, which generates the packet signal by...
6484282 Test pattern generator, a memory testing device, and a method of generating a plurality of test patterns  
A test pattern generator for generating a plurality of test patterns to test a memory comprising: a control memory for storing plural kinds of control instructions to generate the test patterns; a...
6467056 Semiconductor integrated circuit and method of checking memory  
A test circuit comprised of a microprogram controlled control unit for generating a test pattern (addresses and data) for each memory in accordance with a predetermined algorithm and reading...
6438719 Memory supervision  
A method and system for testing a memory in operation. A storage unit is used to temporarily free one memory location in the memory, making it possible to check this memory location for bit errors....
6434503 Automated creation of specific test programs from complex test programs  
A method for providing specific test programs from a production test program for testing semiconductor devices, in accordance with the present invention, includes providing a semiconductor device...
6425099 Method of updating an associative memory of the TRIE type, and router implementing such a method  
An associative memory of the TRIE type is organised in the form of registers of 2 K cells having a portal register from which binary strings are analyzed in successive slices of K bits. Each...
6389525 Pattern generator for a packet-based memory tester  
A pattern generator for use in a memory tester to provide packet address and data signals to a packet-based memory-under-test is disclosed. The pattern generator includes an address source for...
6385746 Memory test circuit  
A memory test circuit having access control circuits ( 11 and 12, or 21 and 22, or 31 and 32 ) recognizes a first memory circuit ( 101 ) and a second memory circuit ( 102 ), as one...
6345372 Method for testing bus connections of writable and readable integrated electronic circuits, in particular memory components  
A method for testing bus connections of electronic circuits, in particular memory components, selects address and data bit test patterns such that, in a first step of write and read steps,...
6343161 Image processing device  
Image data of a test pattern is transmitted to an image processor and image processing is effected by the image processor based on the test pattern. The image outputted (the results of the image...
6333872 Self-test method for testing read stability in a dual-port SRAM cell  
A structure and method for testing multi-port SRAM cells includes a test controller connected to at least one multi-port SRAM cell (the test controller is adapted to store a pattern into the...
6330696 Self-testing of DRAMs for multiple faults  
DRAM memory unit is tested for a series of cell faults such as: the stuck-at fault (SAF), the stuck-open fault (SOF), the transition fault (TF), the multiple address fault (MAF) as well as storage...
6327198 Semiconductor memory device having a test mode setting circuit  
A semiconductor memory device according to the present invention includes: a test mode setting circuit capable of serially setting a plurality of test modes in accordance with an external signal; a...
6323664 Semiconductor memory device capable of accurately testing for defective memory cells at a wafer level  
Disclosed herein is a semiconductor memory device that includes a memory cell array and a plurality of pads for providing data to and from the memory cell array. A plurality of input/output line...
6317852 Method to test auto-refresh and self refresh circuitry  
This invention describes a method to test both auto-refresh and self refresh of an SDRAM. The method writes a logical zero in to a single cell on each word line using a write with auto-precharge...
6317851 Memory test circuit and a semiconductor integrated circuit into which the memory test circuit is incorporated  
A memory test circuit in which time required for a memory test is reduced is disclosed. A memory test circuit according to the present invention is provided with stripe data generating means for...
6286116 Built-in test method for content addressable memories  
A method and apparatus for built in self test, BIST, of content addressable memory, CAM, and associated random access memory, RAM, is described. The method and apparatus may most beneficially be...
6279128 Autonomous system for recognition of patterns formed by stored data during computer memory scrubbing  
A system for continuous monitoring and autonomous detection of patterns in the main memory subsystem of a computer system. The invention can be embodied as an extension to existing memory scrubbing...
6237116 Testing error correcting code feature in computers that do not have direct hardware features for causing single bit and multi-bit errors  
Built-in tests included in reset functions of single board computers can be rapidly performed to confirm adequate functionality without additional hardware support by disabling an error correcting...
6233669 Memory address generator capable of row-major and column-major sweeps  
An improved method and structure for generating addresses of a memory array facilitates the testing of a memory cell by generating the address of any adjacent memory cell to the memory cell under...
6219807 Semiconductor memory device having an ECC circuit  
To provide a semiconductor memory device having an ECC circuit whereof checker-data inspection of memory cells in the user areas and the ECC areas can be performed at once, the ECC code generation...
6219467 Image processing device  
A test pattern which has an outputted image obtained by said image processing executing normal image processing is used to self-judge an image processor. Namely, image data of the above described...
6195771 Semiconductor device having semiconductor memory circuit to be tested, method of testing semiconductor memory circuit and read circuit for semiconductor memory circuit  
Disclosed herein is a semiconductor device having a semiconductor memory circuit whose operation is tested in combination with an external test means to specify defective portions produced in a...
6182262 Multi bank test mode for memory devices  
A multiple bank memory device is described which can be tested by accessing the multiple memory banks simultaneously. The memory includes a test mode trigger which initiates a test which writes and...
6170070 Test method of cache memory of multiprocessor system  
A test method for a cache memory of a multiprocessor system. The multiprocessor system has a shared memory structure accessed via a system bus, including a multiplicity of processor modules, each...
6167542 Arrangement for fault detection in circuit interconnections  
Testing time of interconnections is reducted by splitting up the collection of connection paths to be tested into two or more groups. A set of test vectors, which is applied to each of the groups...
6148424 Pattern generating apparatus  
A pattern generating apparatus used in quality judgment testing of memories incorporating a predetermined signal transfer configuration such as a protocol transfer system, the apparatus having: an...
6112322 Circuit and method for stress testing EEPROMS  
A circuit and method are provided for stress-testing EEPROMS by incrementally selecting and deselecting word lines. The circuit of the invention comprises a memory cell array, a set of decoders for...
6081910 Circuit for allowing a two-pass fuse blow to memory chips combining an array built-in self-test with redundancy capabilities  
A circuit that enhances the testability of an integrated circuit of a memory type and which identifies defective redundant word lines in a state of the art SRAM macro that combines an ABIST...
6079037 Method and apparatus for detecting intercell defects in a memory device  
A method for identifying intercell defects in a memory device activates a plurality of spaced-apart rows simultaneously. Each of the rows includes cells that are written to logic states...
6065143 Semiconductor memory device capable of fast testing without externally considering address scramble or data scramble  
A row address signal output from an internal row address generation circuit according to an output from a ring oscillator activated in response to an externally applied burn-in mode designation...
6035420 Method of performing an extensive diagnostic test in conjunction with a bios test routine  
A BIOS testing routine is initiated. Control is transferred to a diagnostic routine. The diagnostic routine performs a series of test in which a plurality of components are examined. In one...
6032275 Test pattern generator  
It is to provide a test pattern generator that can easily generate expected value data for arbitrary initial values when testing a memory device having a function of write enable/disable control...
6016561 Output data compression scheme for use in testing IC memories  
A memory system operable in a normal mode of operation and a test mode of operation includes sensing circuitry which generates x number of data bits during a read cycle. A read path circuit,...
6009541 Apparatus for performing an extensive diagnostic test in conjunction with a bios test routine  
A BIOS testing routine is initiated. Control is transferred to a diagnostic routine. The diagnostic routine performs a series of test in which a plurality of components are examined. In one...
5996106 Multi bank test mode for memory devices  
A multiple bank memory device is described which can be tested by accessing the multiple memory banks simultaneously. The memory includes a test mode trigger which initiates a test which writes and...
5991904 Method and apparatus for rapidly testing memory devices  
A circuit transfers data in an array of memory cells arranged in rows and columns. The circuit includes a plurality of row lines, a plurality of pairs of complementary digit lines, and an array of...
5987636 Static test sequence compaction using two-phase restoration and segment manipulation  
A technique for static compaction of test sequences is described. The method for static compaction according to the present invention includes two key features: (1) two-phase vector restoration,...
Matches 51 - 100 out of 205 < 1 2 3 4 5 >