|
Match
|
Document |
Document Title |
|
|
7624317 |
Parallel bit test circuit and method for semiconductor memory device
A semiconductor memory device performs a parallel bit test on a plurality of memory blocks by writing test pattern data into the plurality of memory blocks, outputting two bits from each memory...
|
|
|
7620876 |
Reducing false positives in configuration error detection for programmable devices
A device reduces false positive memory error detections by using a masking unit and sensitivity mask data to exclude unused portions of the memory from the error detection computations. A device...
|
|
|
7620861 |
Method and apparatus for testing integrated circuits by employing test vector patterns that satisfy passband requirements imposed by communication channels
Embodiments of an apparatus and method for high-speed testing of a device under test are described herein, where the device under test is coupled to a tester via a limited passband communication...
|
|
|
7620853 |
Methods for detecting resistive bridging faults at configuration random-access memory output nodes
Integrated circuits such as programmable logic device integrated circuits have configuration random-access memory elements. The configuration random-access memory elements are tested to determine...
|
|
|
7620792 |
Processing system, memory and methods for use therewith
A memory includes an array of memory cells arranged in a plurality of rows and a plurality of columns. An address transform module receives a logical address including a logical column address and...
|
|
|
7617431 |
Method and apparatus for analyzing delay defect
The apparatus for analyzing a delay defect of the present invention obtains the RC of the maximal incidence among region codes (RCs) to which check circuits detecting errors caused with gradual...
|
|
|
7617425 |
Method for at-speed testing of memory interface using scan
A method and a circuit of testing of a memory interface associated with an embedded memory in a semiconductor circuit involves writing to two memory locations in succession; reading the two memory...
|
|
|
7613975 |
Predictive diagnosis of a data read system
A data read system comprising a read channel for processing a signal, and a diagnostic controller in communication with the read channel. The diagnostic controller is configured to measure at least...
|
|
|
7610433 |
Memory controller interface
A memory interface controller and method to allow a processor designed and configured to operate with NOR flash and static random access memory (SRAM) memory devices to instead operate using NAND...
|
|
|
7607060 |
System and method for performing high speed memory diagnostics via built-in-self-test
A system and method for performing high speed memory diagnostics via built-in-self-test (BIST). A test system includes a tester for testing an integrated circuit that includes a BIST circuit and a...
|
|
|
7607055 |
Semiconductor memory device and method of testing the same
A semiconductor memory device includes at least one first built in self test (BIST) circuit configured to generate test pattern data, and at least one second BIST circuit configured to receive the...
|
|
|
7603596 |
Memory device capable of detecting its failure
A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for...
|
|
|
7603595 |
Memory test circuit and method
A memory test circuit according to an embodiment of the invention executes a test on a memory in accordance with a pattern mode signal designating a sub-test pattern included in a test pattern and...
|
|
|
7596729 |
Memory device testing system and method using compressed fail data
A memory device testing system includes a signal generator providing memory command, address and write data signal to write data in a memory device and then read the data from the memory device....
|
|
|
7577885 |
Semiconductor integrated circuit, design support software system and automatic test pattern generation system
A semiconductor integrated circuit has a memory circuit having memory cells, a first register, a second register, a register selection circuit having an input to which an output of the first...
|
|
|
7577690 |
Managing checkpoint queues in a multiple node system
Techniques are provided for managing caches in a system with multiple caches that may contain different copies of the same data item. Specifically, techniques are provided for coordinating the...
|
|
|
7574636 |
Semiconductor memory device
The present invention provides a semiconductor memory device comprising a memory cell array including a plurality of memory regions, an address decoding portion for decoding an address applied from...
|
|
|
7574635 |
Circuit for and method of testing a memory device
Circuit and methods for testing a memory device are disclosed. According to one aspect of the invention, a circuit for testing an asynchronous data transfer comprises a first circuit receiving a...
|
|
|
7574633 |
Test apparatus, adjustment method and recording medium
There is provided a test apparatus that tests a device under test including a plurality of data terminals and a clock output terminal, the test apparatus including a plurality of first variable...
|
|
|
7565586 |
Method and apparatus for latent fault memory scrub in memory intensive computer hardware
A method for operating a memory checker in a command monitoring architecture comprising at least two processing lanes comprises a first step of receiving a command to activate a first test mode....
|
|
|
7562269 |
Semiconductor storage device
A testing device for a semiconductor storage device which suppresses the increase in the circuit size, provides for facilitated accommodation to a test with frequent changes in the test pattern,...
|
|
|
7558992 |
Reducing the soft error vulnerability of stored data
Embodiments of apparatuses and methods for reducing the soft error vulnerability of stored data are disclosed. In one embodiment, an apparatus includes storage logic, determination logic, and...
|
|
|
7558941 |
Automatic detection of micro-tile enabled memory
In one embodiment of the invention, a write cache line with a unique bit pattern is written into memory in a memory channel at a starting address. An attempt is made to enable micro-tile memory...
|
|
|
7552368 |
Systems and methods for simultaneously testing semiconductor memory devices
A method for testing a memory cell array of a semiconductor memory device in a parallel bit test mode includes selecting first data from one of a plurality of memory regions in the memory array for...
|
|
|
7549086 |
Memory card and its initial setting method
In the initial setting of a memory card 1 , the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD 1 1 stored previously in...
|
|
|
7546497 |
Semiconductor memory device and data write and read method thereof
A semiconductor memory device includes a serial to parallel converter configured to generate parallel data at a parallel data rate in response to first serial data at first serial data rate in a...
|
|
|
7543198 |
Test data reporting and analyzing using data array and related data analysis
Reporting and/or analyzing test data from a plurality of tests of an array structure using a data array. One method includes obtaining the test data, and reporting the test data in a data array,...
|
|
|
7543176 |
Background consistency checking in an optical transceiver
A method that enables an optical transceiver (or optical transmitter or optical receiver) to perform consistency checking such as Cyclic Redundancy Checking (CRC) in the background while the...
|
|
|
7539923 |
Circuit and method of transmitting a block of data
A circuit for transmitting a block of data is disclosed. The circuit comprises a memory array having a plurality of memory locations coupled to receive data; a first data source coupled to the...
|
|
|
7536614 |
Built-in-redundancy analysis using RAM
A method for testing memory in an integrated circuit device is disclosed. The method includes executing a test routine in a portion of the memory at a speed sufficient to fully test the memory...
|
|
|
7533310 |
Semiconductor memory test device and method thereof
A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory...
|
|
|
7529989 |
Testing apparatus and testing method
A testing apparatus according to the present invention includes: a pattern generator for generating an address signal, a data signal and an expected value signal to be provided to a memory under...
|
|
|
7529864 |
Method and system for testing remote I/O functionality
A method and system for testing a remote I/O sub-assembly. The method including: allocating source memory, destination memory and DMA queue memory location in a memory of the remote I/O...
|
|
|
7526690 |
Semiconductor device-testing apparatus
A semiconductor device-testing apparatus which is capable of testing semiconductor devices simultaneously by a simple construction. A plurality of latch circuits latch output signals outputted from...
|
|
|
7526683 |
Dynamic self-tuning soft-error-rate-discrimination for enhanced availability of enterprise computing systems
A method for use in a computer system provides a dynamic, “self tuning” soft-error-rate-discrimination (SERD) method and apparatus. Specially designed SRAMs or other circuits are “tuned” in...
|
|
|
7523367 |
Method and apparatus to verify non-deterministic results in an efficient random manner
The present invention is directed to a system, method and article of manufacture for testing and design verification of hardware devices by providing for random accesses to the registers of a...
|
|
|
7519886 |
Apparatus and method for integrated functional built-in self test for an ASIC
We describe, in exemplary embodiments, an on-chip Functional Built-In Self Test (“FBIST”) mechanism for testing integrated circuits with internal memory state and complex transaction based...
|
|
|
7512847 |
Method for estimating and reporting the life expectancy of flash-disk memory
A method for managing a memory device, a memory device so managed and a system that includes such a memory device. A value of a longevity parameter of the device is monitored after a data operation...
|
|
|
7509547 |
System and method for testing of interconnects in a programmable logic device
Methods and systems provide for early and simplified testing for defects in the interconnects of a programmable logic device (PLD) and in associated software tools. Data that describes the...
|
|
|
7509545 |
Method and system for testing memory modules
A method and system for testing memory modules is disclosed. The system includes a memory module and a connector configured to receive the module. The memory module is configured to operate in two...
|
|
|
7506226 |
System and method for more efficiently using error correction codes to facilitate memory device testing
A memory device includes an ECC and test circuit. In a normal mode, the circuit performs ECC conventional functions. In a test mode, the least significant bit of received data is used to generate...
|
|
|
7490279 |
Test interface for random access memory (RAM) built-in self-test (BIST)
Built-In Self Test (BIST) is a test technique wherein semiconductor integrated circuit devices test themselves during their operation lifetime. BIST techniques do not necessarily require additional...
|
|
|
7490274 |
Method and apparatus for masking known fails during memory tests readouts
Embodiments of the present invention generally provide methods and apparatus for testing memory devices having normal memory elements and redundant memory elements. During a front-end testing...
|
|
|
7490196 |
Data backup using both tape and disk storage
A magnetic tape apparatus for backup stores data provided from a computer on a magnetic tape. A writing circuit writes data provided from the computer on the magnetic tape, and switches a writing...
|
|
|
7484144 |
Testing embedded memory in an integrated circuit
An integrated circuit includes a first bus and at least one array of embedded memories. Each array includes a second bus such as a bidirectional bus coupled to the embedded memories and to the...
|
|
|
7484140 |
Memory having variable refresh control and method therefor
A memory ( 10 ) has a memory array ( 12 ), a charge pump ( 18 ), a voltage regulator ( 20 ), a refresh control circuit ( 16 ), and a refresh counter ( 22 ). The charge pump ( 18 ) provides a...
|
|
|
7478300 |
Method for testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device
A method for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device is provided. With the method, each clock domain has its own scan paths that do not...
|
|
|
7475315 |
Configurable built in self test circuitry for testing memory arrays
Integrated circuits such as programmable logic device integrated circuits are provided that have memory arrays. The memory arrays can be tested using configurable built in self test circuitry. The...
|
|
|
7475300 |
Test circuit and test method
A test method sets a write value to a scan flip-flop for setting a value to a memory to be tested. It then performs a series of shift operation in scan paths until setting of a read value is...
|
|
|
7464309 |
Method and apparatus for testing semiconductor memory device and related testing methods
A test method and apparatus for a semiconductor memory device is characterized by the sequentially programmed use of two test different modes. A first test mode tests at least signal line integrity...
|