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9135111 Nonvolatile memory device and bad area managing method thereof  
Example embodiments relate to a bad area managing method of a nonvolatile memory device. The nonvolatile memory device may include a plurality of memory blocks and each block may contain memory...
9043662 Double data rate memory physical interface high speed testing using self checking loopback  
A double data rate memory physical interface having self checking loopback logic on-chip is disclosed. Disposed on the chip is a first linear feedback shift register, which is capable of...
9043661 Memories and methods for performing column repair  
Memory devices adapted to repair single unprogrammable cells during a program operation, and to repair columns containing unprogrammable cells during a subsequent erase operation. Programming of...
9043663 Apparatus and method for testing a memory  
An apparatus is equipped with a storage device including an error correction circuit. The apparatus performs a test of the storage device according to a predetermined testing procedure, and...
9036437 Method and apparatus for testing memory utilizing a maximum width of a strobe signal and a data width of a data signal  
A method and an apparatus for testing a memory are provided, and the method is adapted for an electronic apparatus to test the memory. In the method, a left edge and a right edge of a first...
9037931 Methods and systems for logic device defect tolerant redundancy  
Provided is an apparatus including a scheduler and a plurality of logic devices coupled to the scheduler, each including a defect indicator. The scheduler determines whether one or more of the...
9030339 Transmitting device and receiving device  
A transmitting device includes a parallel data generation unit and a transmitting unit. The parallel data generation unit generates first serial data and second serial data from a data packet,...
9032262 Memory test method, memory test device, and adapter thereof  
A memory test device used to test performance of at least one memory module on an electronic device, are provided. The memory test device includes at least one adapter and a control unit. The...
9026869 Importance-based data storage verification  
Methods and systems for detecting error in data storage entities based at least in part on importance of data stored in the data storage entities. In an embodiment, multiple verification passes...
9026870 Memory module and a memory test system for testing the same  
A memory module includes a first rank, a second rank and a test control unit. The first rank includes a plurality of semiconductor memory devices configured to operate in response to a first chip...
9021293 Methods for operating a memory interface circuit including calibration for CAS latency compensation in a plurality of byte lanes  
A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface...
9021321 Testing disk drives shared by multiple processors in a supercomputer complex  
An interface node selects a logical block address that corresponds to a contiguous memory location located on a storage device that is accessible by multiple interface nodes. The interface node...
9021320 pBIST architecture with multiple asynchronous sub chips operating in differing voltage domains  
A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories may be operating at a voltage domain different from the voltage domain of the pBIST. A plurality...
9015537 Bit error rate based wear leveling for solid state drive memory  
According to exemplary embodiments, a system, is provided for bit error rate (BER)-based wear leveling in a solid state drive (SSD). A block-level BER value for a block in the SSD is determined....
9015546 Automatic retransmission request control system and retransmission method in mimo-OFDM system  
An automatic retransmission request control system in an OFDM-MIMO communication system includes a retransmission mode selection part which selects a retransmission mode from among (a) a mode in...
9015539 Testing of non stuck-at faults in memory  
A method for identifying non stuck-at faults in a read-only memory (ROM) includes generating a golden value of a victim cell, providing a fault-specific pattern through an aggressor cell,...
9009548 Memory testing of three dimensional (3D) stacked memory  
A method includes reading, at a memory controller, data from a first dynamic random-access memory (DRAM) die layer of a DRAM stack. The method also includes writing the data to a second DRAM die...
9009549 Memory diagnostic apparatus and memory diagnostic method and program  
A RAM to be diagnosed is divided into n (n being an integer of 3 or greater) pieces of base regions. In an idle time of periodic processing performed in a system in which the RAM is incorporated,...
9009547 Advanced programming verification schemes for analog memory cells  
A method for data storage includes receiving in a memory device data for storage in a group of analog memory cells. The data is stored in the group by performing a Program and Verify (P&V)...
9009565 Systems and methods for mapping for solid-state memory  
Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state...
9003255 Automatic test-pattern generation for memory-shadow-logic testing  
An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory...
9003262 Memory controller, devices including the same, and operating method thereof  
An operating method of a memory controller includes classifying a plurality of blocks in a memory cell array included in a flash memory into a first group and a second group according to the...
9003246 Functional memory array testing with a transaction-level test engine  
A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine...
8996936 Enhanced error correction in memory devices  
A method of correcting stored data includes reading data stored in a portion of a nonvolatile memory. The method includes, for each particular bit position of the read data, updating a count of...
8996934 Transaction-level testing of memory I/O and memory device  
A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine...
8996959 Adaptive copy-back method and storage device using same  
During a garbage collection process for a non-volatile memory device of a storage device, an adaptive copy-back method selectively performs either an external or an internal copy-back operation in...
8996933 Memory management method, controller, and storage system  
An identification code generation method and a management method for a non-volatile memory, and a controller and a storage system using the same are provided, and the non-volatile memory has a...
8996935 Memory operation of paired memory devices  
A method and apparatus for operation of a memory module for storage of a data word is provided. The apparatus includes a memory module having a set of paired memory devices including a first...
8990607 Memory interface circuits including calibration for CAS latency compensation in a plurality of byte lanes  
A memory interface circuit for read operations is described. The circuit includes one or more controller circuits, one or more read data delay circuits for providing CAS latency compensation for...
8990491 Eye scan for asymmetric shaped communication signal  
Techniques for processing signal information from a high speed communication bus. The techniques includes determining spatial regions on an eye characterized by a start point, an end point, a...
8990647 Memory devices and methods for managing error regions  
Memory devices and methods include a stack of memory dies and a logic die. Method and devices include those that provide for repartitioning the stack of memory dies and storing the new partitions...
8984370 Secondary memory to store error correction information  
A system and method are disclosed in which a first non-volatile memory includes blocks that store data, and a second memory that stores error correction information related to the blocks storing...
8984353 Information storage device and test method of setting a test condition for information storage device outside range of presupposed real use conditions  
A method of testing the operational margin of an information storage device having marked random variations, and an information storage device having the function of self-diagnosing the...
8984354 Test system which shares a register in different modes  
A test system, comprising: a BIST circuit for generating a first signal; a storage apparatus, for storing the first signal to generate a second signal; a first logic circuit, for generating a...
8977915 pBIST engine with reduced SRAM testing bus width  
A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module....
8977914 Stress-based techniques for detecting an imminent read failure in a non-volatile memory array  
A technique for detecting an imminent read failure in a non-volatile memory array includes applying a bulk read stress to a plurality of cells of the non-volatile memory array and determining...
8977912 Method and apparatus for repairing memory  
Methods and apparatuses are disclosed in which a repair instruction, such as from a tester, causes an integrated circuit undergoing testing to substitute defective locations of a first set of...
8977930 Memory architecture optimized for random access  
In an embodiment, a plurality of memory dies is coupled as a memory block. The memory block has an access width defined as a system word length divided by a burst length associated with the...
8972821 Encode and multiplex, register, and decode and error correction circuitry  
An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the processor and the peripheral to...
8971138 Method of screening static random access memory cells for positive bias temperature instability  
A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for n-channel...
8972824 Systems and methods for transparently varying error correction code strength in a flash drive  
Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state...
8966331 Test circuit of semiconductor memory apparatus and semiconductor memory system including the same  
A semiconductor memory apparatus includes a test circuit configured to receive a plurality of sequentially-changing test input patterns, compress the received test input patterns at each clock...
8966348 Memory error identification based on corrupted symbol patterns  
A system includes a memory controller, a buffer, a first channel to couple the memory controller to the buffer, and a second channel to couple the buffer to a memory. The first channel and second...
8966328 Detecting a memory device defect  
A technique includes receiving data indicative of a time varying count of errors, which are attributable to at least one memory device. The technique includes filtering the indicated count and...
8954825 Apparatuses and methods including error correction code organization  
Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory cells, and a second access line...
8949692 Method and system for service-aware parity placement in a storage system  
A method and system for service-aware parity placement in a storage system, including after receiving the service notification specifying a target SD: writing a RAID stripe to the persistent...
8947957 Built-in self repair for memory  
A method for repairing a memory includes running a built-in self-test of the memory to find faulty bits. A first repair result using a redundant row block is calculated. A second repair result...
8949679 Memory buffer for buffer-on-board applications  
Disclosed in a method of optimizing a voltage reference signal. The method includes: assigning a first value to the voltage reference signal; executing a test pattern while using the voltage...
8949689 Storage control system with data management mechanism and method of operation thereof  
A method of operation of a storage control system includes: generating encoded data having a proportional data distribution for writing to a memory device; identifying a marginal block when an...
8943457 Simulating scan tests with reduced resources  
An aspect of the present invention replaces memory elements in a scan chain with corresponding new (memory) elements, with each new element having two paths to provide the corresponding data...