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7624317 |
Parallel bit test circuit and method for semiconductor memory device
A semiconductor memory device performs a parallel bit test on a plurality of memory blocks by writing test pattern data into the plurality of memory blocks, outputting two bits from each memory...
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7624316 |
Apparatus and method for testing removable flash memory devices
A memory device may include a controller and a plurality of flash memory dice. The controller is provided for read and write access and communications with a host. However, the controller may also...
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7624315 |
Adapter card for connection to a data bus in a data processing unit and method for operating a DDR memory module
One embodiment of the invention provides an adapter card for connection to a data bus in a data processing unit. The adapter includes a DDR interface for connection of a DDR memory module, a memory...
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7624313 |
TCAM BIST with redundancy
In an embodiment of the invention, a method of providing redundancy in a ternary content addressable memory (TCAM) includes: detecting a defective entry in a ternary content addressable memory...
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7620861 |
Method and apparatus for testing integrated circuits by employing test vector patterns that satisfy passband requirements imposed by communication channels
Embodiments of an apparatus and method for high-speed testing of a device under test are described herein, where the device under test is coupled to a tester via a limited passband communication...
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7620859 |
Filtered register architecture to generate actuator signals
In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced register including a first memory...
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7617425 |
Method for at-speed testing of memory interface using scan
A method and a circuit of testing of a memory interface associated with an embedded memory in a semiconductor circuit involves writing to two memory locations in succession; reading the two memory...
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7613962 |
Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application
The present invention provides a circuit and a method for the full speed testing of semiconductor memory chips. The invention provides a full-speed data transition scheme for double data rate (DDR)...
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7613961 |
CPU register diagnostic testing
One embodiment disclosed relates to a method of compiling a program to be executed on a target central processing unit (CPU). The method includes opportunistically scheduling diagnostic testing of...
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7613960 |
Semiconductor device test apparatus and method
There is provided a semiconductor test apparatus which uses a test processor to apply a test signal to a DUT having a semiconductor device within it to determine whether the memory is acceptable or...
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7610528 |
Configuring flash memory
A system for configuring or testing memory may cycle a memory array while substantially concurrently performing other functional testing. In particular implementations, the system may configure, or...
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7610524 |
Memory with test mode output
Methods of operating an apparatus allow a memory to generate a test mode signal to trigger a test, in response to the memory detecting a predetermined command from a system bus.
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7610523 |
Method and template for physical-memory allocation for implementing an in-system memory test
An in-system memory testing method includes transparently selecting and “stealing” a portion of memory from the memory system for running memory tests, then running one or more of the numerous...
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7607056 |
Semiconductor test apparatus for simultaneously testing plurality of semiconductor devices
Disclosed herein is a semiconductor test apparatus for simultaneously testing a plurality of semiconductor devices. The semiconductor test apparatus includes a plurality of pattern generation...
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7607055 |
Semiconductor memory device and method of testing the same
A semiconductor memory device includes at least one first built in self test (BIST) circuit configured to generate test pattern data, and at least one second BIST circuit configured to receive the...
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7607048 |
Method and apparatus for protecting TLB's VPN from soft errors
A method and apparatus for protecting a TLB's VPN from soft errors is described. On a TLB lookup, the incoming virtual address is used to CAM the TLB VPN. In parallel with this CAM operation,...
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7603603 |
Configurable memory architecture with built-in testing mechanism
A configurable memory architecture includes a built-in testing mechanism integrated in said memory to support very efficient built-in self-test in Random Access Memories (RAMs) with greatly reduced...
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7603600 |
Timing failure remedying apparatus for an integrated circuit, timing failure diagnosing apparatus for an integrated circuit, timing failure diagnosing method for an integrated circuit, integrated circuit, computer readable recording medium recorded thereon a timing failure diagnosing program for an integrated circuit, and computer readable recording medium recorded thereon a timing failure remedying program for an integrated circuit
A timing failure remedying apparatus for an integrated circuit has a comparator which compares a value captured in a taking-out scan chain for reference through an operation of a processing core...
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7603596 |
Memory device capable of detecting its failure
A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for...
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7603595 |
Memory test circuit and method
A memory test circuit according to an embodiment of the invention executes a test on a memory in accordance with a pattern mode signal designating a sub-test pattern included in a test pattern and...
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7603593 |
Method for managing bad memory blocks in a nonvolatile-memory device, and nonvolatile-memory device implementing the management method
A method for managing bad memory blocks of a nonvolatile-memory device, in which the available memory blocks are divided into a first set, formed by addressable memory blocks that are to be used by...
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7603246 |
Data interface calibration
Embodiments for positioning transitions in one or more data signals in relation to a data strobe signal are disclosed. For an example embodiment, a receiving device may return a test value to a...
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7602171 |
System for testing memory modules using a rotating-type module mounting portion
A system for testing memory modules having a rotating-type board mounting portion with a plurality of mounting surfaces positioned at different planes and connected around an axis to form a...
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7600167 |
Flip-flop, shift register, and scan test circuit
A flip-flop has a first latch and a second latch. The first latch has a first feedback circuit and a first selecting circuit which selects one of a first data input signal and an output signal of...
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7596729 |
Memory device testing system and method using compressed fail data
A memory device testing system includes a signal generator providing memory command, address and write data signal to write data in a memory device and then read the data from the memory device....
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7594148 |
Apparatus and method for testing semiconductor memory device
A semiconductor memory device for performing a reliability test includes a write driving block for generating a predetermined test voltage in a test mode and delivering a data inputted from an...
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7590903 |
Re-configurable architecture for automated test equipment
An adaptive test system includes one or more reconfigurable test boards, with each test board including at least one re-configurable test processor. The re-configurable test processors can transmit...
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7590899 |
Processor memory array having memory macros for relocatable store protect keys
A DDR SDRAM DIMM for a mainframe main storage subsystem has a plurality of DDR SDRAMs on a rectangular printed circuit board having a first side and a second side, a length (152 MM=6 inch) between...
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7587655 |
Method of transferring signals between a memory device and a memory controller
Method and apparatus for communication (e.g., transmitting and/or receiving) command, address and data signals from a memory device to a memory controller or vice versa. The data signals are...
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7587645 |
Input circuit of semiconductor memory device and test system having the same
An input circuit of a semiconductor memory device includes a data input circuit and a data pattern setting circuit. The data input circuit receives first data, and generates second data by...
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7584391 |
Smart verify for multi-state memories
A “smart verify” technique, whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify...
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7584390 |
Method and system for alternating between programs for execution by cells of an integrated circuit
A method and device for data processing in an integrated circuit having cells, the cells adapted for executing programs. A first program is run. In response to a waiting condition during which no...
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7584384 |
Method and apparatus for enabling and disabling a test mode of operation of an electronic memory device without additional interconnects or commands
A method and apparatus allows an electronic device to operate, first, in a test mode and, second, in a functional mode, the functional mode being the normal operating mode of the device. In the...
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7581146 |
Semiconductor memory device storing repair information avoiding memory cell of fail bit operating method thereof
A semiconductor memory device including a memory array having a plurality of memory cells and a data input/output unit. A part of the memory array is assigned as a repair information region. The...
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7577885 |
Semiconductor integrated circuit, design support software system and automatic test pattern generation system
A semiconductor integrated circuit has a memory circuit having memory cells, a first register, a second register, a register selection circuit having an input to which an output of the first...
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7577884 |
Memory circuit testing system, semiconductor device, and memory testing method
A semiconductor device that performs refresh tests of a plurality of individual memories built into the same chip and prevents excessive testing during the refresh test. When a first testing...
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7577882 |
Semiconductor integrated circuit including memory macro
The present invention provides a semiconductor integrated circuit having area efficiency and repair efficiency improved by sharing a redundant memory macro among a plurality of SRAM macros. Each of...
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7574634 |
Real time testing using on die termination (ODT) circuit
A system and method to operate an electronic device, such as a memory chip, in a test mode using the device's built-in ODT (on die termination) circuit is disclosed. One or more test mode related...
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7574633 |
Test apparatus, adjustment method and recording medium
There is provided a test apparatus that tests a device under test including a plurality of data terminals and a clock output terminal, the test apparatus including a plurality of first variable...
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7571407 |
Semiconductor integrated circuit and method of testing delay thereof
A semiconductor integrated circuit comprises: a first area, formed on a semiconductor chip, which operates at a first predetermined voltage and a first predetermined frequency; a second area,...
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7571367 |
Built-in self diagnosis device for a random access memory and method of diagnosing a random access
A self diagnosis (BISD) device for a random memory array, preferably integrated with the random access memory, executes a certain number of predefined test algorithms and identifies addresses of...
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7568135 |
Use of alternative value in cell detection
A system and method, including computer software, allows reading data from a flash memory cell. Voltages from a group of memory cells are detected. The group of memory cells have associated...
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7568134 |
Method of exhaustively testing an embedded ROM using generated ATPG test patterns
A model of the memory device is provided, including a memory array model having a plurality of memory array model locations, and a plurality of decoder models, each associated with a memory array...
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7565588 |
Semiconductor device and data storage apparatus
A semiconductor device and a data storage apparatus are provided. A semiconductor device includes: a cell array configured to have cells for data storage arranged in an array; at least one buffer...
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7565587 |
Background block erase check for flash memories
Memory devices and methods of operating memory devices provide for using differing potentials during erase verify operations facilitate normal erase operations and subsequent erase check...
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7565586 |
Method and apparatus for latent fault memory scrub in memory intensive computer hardware
A method for operating a memory checker in a command monitoring architecture comprising at least two processing lanes comprises a first step of receiving a command to activate a first test mode....
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7565585 |
Integrated redundancy architecture and method for providing redundancy allocation to an embedded memory system
An integrated redundancy architecture for an embedded memory system whereby a third memory element is added to the redundancy architecture such that all row and column fails may be stored in...
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7562268 |
Method and apparatus for testing a memory device with compressed data using a single output
A method and apparatus for testing a memory device with compressed data using multiple clock edges is disclosed. In one embodiment of the present invention data is written to cells in a memory...
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7562267 |
Methods and apparatus for testing a memory
In a first aspect, a first method is provided that includes the steps of (1) transmitting a first signal representative of a test operation from a test circuit to a memory via a first signal path;...
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7562263 |
System and method for detecting and recovering from errors in a control store of an electronic data processing system
A system and method are provided for detecting and recovering from errors in a control store memory of an electronic data processing system. In some cases, errors in the control store memory are...
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