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8843794 Method, system and apparatus for evaluation of input/output buffer circuitry  
Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a...
8817635 Methods, test systems and arrangements for verifying compliance with requirement specifications  
A method for verifying compliance of a communication device with one or more requirement specifications is disclosed. The method comprises establishing a link between a test system and the...
8782475 PRBS test memory interface considering DDR burst operation  
A method of testing an interconnect between an electronic component and an external memory comprises receiving a data word having data bits and translating the data word into multiple cycles. The...
8638851 Joint bandwidth detection algorithm for real-time communication  
A video coding system and method for increasing a transmitted output bit rate of a video encoding system by altering the content of the bit stream. A video encoder may receive a coding mode signal...
8570857 Resilient IP ring protocol and architecture  
A system and method are disclosed for a resilient IP ring protocol. A system that incorporates teachings of the present disclosure may include, for example, a communication device using a...
8468398 Loopback testing with phase alignment of a sampling clock at a test receiver apparatus  
Methods and test receiver apparatus are provided for loopback testing of a unidirectional physical layer device. The disclosed methods and test receiver apparatus allow for the phase of a sampling...
8234530 Serial interface device built-in self test  
A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test...
8214699 Circuit structure and method for digital integrated circuit performance screening  
Disclosed is a semiconductor chip with a digital integrated circuit, such as a memory device (e.g., static random access memory (SRAM) arrays, dynamic random access memory (DRAM) arrays, content...
8214706 Method and apparatus for testing an electronic circuit integrated with a semiconductor device  
A semiconductor device including an electronic circuit, a memory, and an error detecting module. The electronic circuit is configured to receive an input signal having been generated by a test...
8200850 Method, apparatus and computer program product for ring network communication  
Communication modules are coupled in a communication ring and are operable to send and receive data from peripheral devices. The modules are operable to send and receive data streams on paths of...
8169924 Optimal bridging over MPLS/IP through alignment of multicast and unicast paths  
A provider edge (PE) node of a network operates to send a trace path message over the network to a receiver PE node, the trace path message recording a list of intermediate nodes of a unicast path...
8051350 Serial interface device built-in self test  
A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test...
8001453 CAN system  
Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller...
7958438 CAN system  
Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller...
7934215 Smart scheduler  
A smart scheduler is provided to prepare a machine for a job, wherein the job has specific requirements, i.e., dimensions. One or more config jobs are identified to configure the machine to meet...
7882404 Backplane emulation technique for automated testing  
The present invention implements a method and apparatus for using components within a Serializer/DeSerializer (SerDes) to emulate the effects of a backplane in order to facilitate automated test...
7865789 System and method for system-on-chip interconnect verification  
A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear...
7853850 Testing hardware components to detect hardware failures  
A system for testing hardware components includes a test pattern injector and a test pattern detector coupled to verification paths that pass through hardware components. The test pattern injector...
7792618 Control system and method for a concrete vehicle  
A concrete vehicle is described herein which includes a chassis, a concrete handling system, a vehicle subsystem control system, and a wireless communication system configured to communicate with...
7793171 Protocol tester and method for performing a protocol test  
Embodiments of the present invention provide a protocol tester for performing a protocol test, said protocol tester exhibiting an input for the feeding in of data, a protocol decoding device for...
7783935 Bit error rate reduction buffer  
In a preferred embodiment, the invention provides a circuit for reducing bit error rates. A data recovery circuit recovers data from a first HSS link to differential bit pair inputs. Data from the...
7761764 System and method for self-test of integrated circuits  
A system and method for self-test of an integrated circuit are disclosed. As one example, an integrated circuit is disclosed. The integrated circuit includes a digital signal processing chain, a...
7761753 Memory channel with bit lane fail-over  
Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory...
7685489 Semiconductor integrated circuit and testing method  
A semiconductor integrated circuit includes: an input/output cell that is included in a path captured during propagation delay testing and that has an output-stage buffer on an output bus; and a...
7673207 Method for at speed testing of devices  
A semiconductor device that includes a module under test that is integrated with the semiconductor device, that receives an input signal from a test module, and that provides an output signal to...
7661039 Self-synchronizing bit error analyzer and circuit  
A self-synchronizing data bus analyzer is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a...
7657799 Method and apparatus for testing a dual mode interface  
Disclosed is a system and method for testing a dual mode interface. The dual mode interface includes a first strobe circuit and a second strobe circuit configured to be inoperable during a first...
7653844 Communication apparatus and communication system  
In a communication system based on OSI (Open Systems Interconnection) Reference Model, a pattern body generation circuit of a transmitting device generates and outputs a jitter test pattern body...
7650553 Semiconductor integrated circuit apparatus and interface test method  
An interface test can be performed by, for example, only a self apparatus when interface operation specifications are different between the self apparatus and an original connection partner...
7620861 Method and apparatus for testing integrated circuits by employing test vector patterns that satisfy passband requirements imposed by communication channels  
Embodiments of an apparatus and method for high-speed testing of a device under test are described herein, where the device under test is coupled to a tester via a limited passband communication...
7516374 Testing circuit and related method of injecting a time jitter  
A testing method includes selecting a low-pass filter by simulation, generating testing signals with the low-pass filter receiving output signals of an under-test circuit, and outputting the...
7502975 Data transmission apparatus and method  
A data transmission apparatus comprises an estimation device to estimate a transmission condition of the transmission channel in the transmitter based on at least Jitter information or a packet...
7478298 Method and system for backplane testing using generic boundary-scan units  
A test system for testing a backplane comprising an adapter assembly and a generic boundary-scan test unit. The adapter assembly includes an application-specific mating connector to...
7447862 Memory system and timing control method of the same  
A memory system includes at least one memory module, each of which has a pattern data generating circuit for generating a pattern data, which has a plurality of memories to which a command signal...
7444558 Programmable measurement mode for a serial point to point link  
A serial point to point link that communicatively couples an integrated circuit (IC) device to another IC device is initialized by transferring a training sequence of symbols over the link....
7404115 Self-synchronising bit error analyser and circuit  
A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus...
7398437 Method and system for multi-user channel allocation for a multi-channel analyzer  
Multiple channels of a multi-channel analyzer are allocated among multiple users such that each user can initiate and retrieve the results of separate diagnostic sessions or strategies. Each...
7398438 Method and apparatus for improved routing in connectionless networks  
The invention includes a method and apparatus for determining a routing table for use in a network comprising a plurality of type-one nodes and a plurality of type-two nodes where the type-two...
7380152 Daisy chained multi-device system and operating method  
A multi-device system having a daisy chain system bus structure and related method of operation are disclosed. A reference signal having a defined oscillation period is communicated around the...
7373577 CAN system  
Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller...
7237169 Cross-monitoring sensor system and method  
Cross-monitoring sensor system and method in which a plurality of sensors each having a sensing element, circuitry for processing signals from the sensing element, an output interface for...
7191371 System and method for sequential testing of high speed serial link core  
A testing circuit for testing a series of at least three alternating transmitter and receiver links. The testing circuit including a built-in-self-test (BIST.) macro for generating test data and...
7139925 System and method for dynamic cluster adjustment to node failures in a distributed data system  
A distributed system provides for separate management of dynamic cluster membership and distributed data. Nodes of the distributed system may include a state manager and a topology manager. A...
7055068 Method for validating operation of a fibre link  
A method for validating operation of a fiber link when the fiber link is initialized includes the steps of entering a trial link up state upon receiving a command to initialize the fiber link so...
7054264 Interconnect and gateway protection in bidirectional ring networks  
A communication device for interconnection of first and second networks, of which at least the first network is a bidirectional ring network, includes first and second interconnect modules, each...
7027411 Method and system for identifying and processing changes to a network topology  
A method and system are disclosed for mapping the topology of a network having interconnected nodes by identifying changes in the network and updating a stored network topology based on the...
7020820 Instruction-based built-in self-test (BIST) of external memory  
Disclosed are novel methods and apparatus for efficiently providing instruction-based BIST of external memory. In an embodiment, a built-in self-testing system is disclosed. The system includes an...
7003705 Ethernet automatic protection switching  
A method and apparatus is provided for automatic protection switching in a ring network by creating a protection domain having a control vlan and protected data vlans and designating a master node...
6981186 Loop diagnostic mode for ADSL modems  
A method for establishing communication in an ADSL subscriber loop, the method comprising the steps of determining that showtime cannot be entered during initialization of communication between...
6912679 System and method for electrical data link testing  
A system and method provides for direct control of a high speed data link in a computer system for purposes of testing the data link under a full range of anticipated operating conditions. The...

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