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7620861 Method and apparatus for testing integrated circuits by employing test vector patterns that satisfy passband requirements imposed by communication channels  
Embodiments of an apparatus and method for high-speed testing of a device under test are described herein, where the device under test is coupled to a tester via a limited passband communication...
7620858 Fabric-based high speed serial crossbar switch for ATE  
A loopback module is disclosed in which N differential High Speed Serial (HSS) digital data input channels are received and sent to a serial to parallel converter, whose output is M-bit wide...
7613125 Method and apparatus for temporal alignment of multiple parallel data streams  
Methods and apparatus for aligning the transmitters of two or more bidirectional ports of an integrated circuit (IC), particularly an application-specific IC (ASIC) or field-programmable gate array...
7587202 Method for conducting digital interface and baseband circuitry tests using digital loopback  
In a mobile device having a primary baseband circuit and a secondary baseband circuit and an interface between the primary baseband circuit and a secondary baseband circuit, a method for testing...
7571363 Parametric measurement of high-speed I/O systems  
A phase comparator is used to test a device under test comprising an input/output (I/O) circuit by applying a signal to the device under test; extracting a phase signal from the phase comparator;...
7565587 Background block erase check for flash memories  
Memory devices and methods of operating memory devices provide for using differing potentials during erase verify operations facilitate normal erase operations and subsequent erase check...
7546494 Skew-correcting apparatus using dual loopback  
An apparatus for determining the amount of skew injected into a high-speed data communications system, including a plurality of lanes having a data bus per lane, relative to a reference lane, for...
7529975 Method for testing processor subassemblies  
A method for testing a processor subassembly includes providing a computer system comprising subassemblies. Each subassembly includes processors having internal communication paths and ports that...
7516374 Testing circuit and related method of injecting a time jitter  
A testing method includes selecting a low-pass filter by simulation, generating testing signals with the low-pass filter receiving output signals of an under-test circuit, and outputting the...
7506234 Signature circuit, semiconductor device having the same and method of reading signature information  
A signature circuit in a semiconductor chip includes a signature program circuit configured to be programmed with signature information and to output a signature signal in response to the signature...
7506222 System for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling  
A system for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling includes a slave device and a master device that is coupled to the...
7502975 Data transmission apparatus and method  
A data transmission apparatus comprises an estimation device to estimate a transmission condition of the transmission channel in the transmitter based on at least Jitter information or a packet...
7486121 System and method for generating two effective frequencies using a single clock  
A method and apparatus are disclosed for generating a second clock signal, having a second effective clock frequency, from a first clock signal, having a first effective clock frequency. Clock...
7484155 Analog base-band test apparatus and method by enhanced combination of JTAG and memory in mobile communication system  
An analog base-band (ABB) chipset of a mobile communication system comprises a memory configured to store a test pattern, a test control unit configured to generate a control signal during a test...
7484139 Amplifier fault detection circuit  
An amplifier ( 1 ) adapted to receive an input signal and to generate an output signal at an amplifier output ( 7 ) according to the input signal, the amplifier ( 1 ) comprising: a feedback circuit...
7480840 Apparatus, system, and method for facilitating port testing of a multi-port host adapter  
An apparatus, system, and method are provided for facilitating port testing of a multi-port host adapter. The present invention includes a scheduler that schedules execution of a plurality of...
7478298 Method and system for backplane testing using generic boundary-scan units  
A test system for testing a backplane comprising an adapter assembly and a generic boundary-scan test unit. The adapter assembly includes an application-specific mating connector to communicatively...
7461312 Digital signature generation for hardware functional test  
A Multiple Input Shift Register (MISR) is used to generate signatures, based on data from a device under test, in order to validate the proper sequence and content of the data over a defined period...
7447953 Lane testing with variable mapping  
Memory apparatus and methods selectively map first lanes to second lanes. A memory agent may transfer training and return sequences using different lane mappings. The return sequences may be...
7444558 Programmable measurement mode for a serial point to point link  
A serial point to point link that communicatively couples an integrated circuit (IC) device to another IC device is initialized by transferring a training sequence of symbols over the link....
7426599 Systems and methods for writing data with a FIFO interface  
Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed...
7424649 Latch and phase synchronization circuit using same  
A latch is provided for rapidly stabilizing a latching operation. The latch comprises a first latch circuit for latching a first signal in response to a first portion of a second signal to generate...
7404115 Self-synchronising bit error analyser and circuit  
A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus...
7386767 Programmable bit error rate monitor for serial interface  
A programmable bit error rate monitor includes an error counter, a monitoring period counter with a programmable upper bound to set the monitoring period, and an error flag generator that compares...
7380152 Daisy chained multi-device system and operating method  
A multi-device system having a daisy chain system bus structure and related method of operation are disclosed. A reference signal having a defined oscillation period is communicated around the...
7373577 CAN system  
Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller...
7366964 Method, system, and apparatus for loopback entry and exit  
A loopback test to test a communication link for a layered interface where in a master agent programs the electrical parameters for the slave agent, such as, the offset, timing, and current...
7346819 Through-core self-test with multiple loopbacks  
An integrated circuit device having a test sequence generator, first and second transceivers and a test sequence analyzer. The test sequence generator generates a test data sequence in response to...
7337377 Enhanced loopback testing of serial devices  
A system and method for economically yet thoroughly testing serial ports of electronic devices includes a receiver and a transmitter. The receiver is coupled to a TX line of a device under test for...
7325180 System and method to test integrated circuits on a wafer  
A system to test integrated circuits on a wafer may include a transceiver formed on the wafer. The system may also include an antenna system couplable to the transceiver. The transceiver may be...
7310754 Integrated test circuit, a test circuit, and a test method for performing transmission and reception processing to and from a first and a second macro block at a first frequency  
A macro block MB 2 including a physical-layer circuit PHY for communications performs transmission and reception processing to and from a macro block MB 1 at a clock frequency CF 1 . A test...
7280302 Disk drive using loopback to calibrate transmission amplitude  
A disk drive is disclosed for connecting to a host, the host comprising loopback circuitry operable to loop a pattern received from the disk drive back to the disk drive. The disk drive comprises...
7275195 Programmable built-in self-test circuit for serializer/deserializer circuits and method  
A built-in self-test circuit for use in testing a serializer/deserializer circuit includes a programmable transmit register that transmits data to the serializer/deserializer circuit having...
7272756 Exploitive test pattern apparatus and method  
Communications equipment can be tested using a test pattern that is modified compared to, and more exploitive than, a standard test pattern. Test patterns can be employed that have lengthened or...
7263286 Fast testing system for optical transceiver and testing method thereof  
The present invention provides a fast testing system and method for optical transceiver, which integrates multiple testing machines in the testing environment for the optical transceiver, so that...
7251765 Semiconductor integrated circuit and method for testing a semiconductor integrated circuit  
A semiconductor integrated circuit includes a first delay circuit generating a first delay clock; a second delay circuit generating a second delay clock; a first register registering a value of a...
7231558 System and method for network error rate testing  
An bit error rate tester for use in connection with a high speed networks. The bit error rate tester includes transmit and receive ports, as well as a sequence generator, memory, synchronizer,...
7216269 Signal transmit-receive device, circuit, and loopback test method  
A signal transmit-receive device of the invention reduces the number of high-speed signal lines required for connecting a transmitting circuit group and a receiving circuit group, and for running a...
7203872 Cache based physical layer self test  
A software self test engine is executed from a cache of a processor. The software self test engine is executed using an execution engine of the processor to perform a physical layer self test. The...
7203460 Automated test of receiver sensitivity and receiver jitter tolerance of an integrated circuit  
An automated test system ( 20 ) for testing a high-speed communications integrated circuit ( 10 ), such as a serializer/deserializer, is disclosed. The system ( 20 ) is able to test the parameters...
7191371 System and method for sequential testing of high speed serial link core  
A testing circuit for testing a series of at least three alternating transmitter and receiver links. The testing circuit including a built-in-self-test (BIST.) macro for generating test data and...
7165196 Method for testing serializers/de-serializers  
A test system and method for testing a serializer/de-serializer system. The system includes a pair of serializer/de-serializers each having a serial data receive port and a serial data transmit...
7127648 System and method for performing on-chip self-testing  
A method for determining whether a physical layer device under test is defective may include establishing a closed communication path between a verified physical layer device and the physical layer...
7117402 Background block erase check for flash memories  
A flash memory erase check circuit is disclosed. One embodiment includes an on-chip circuit that quickly and reliably checks that the flash memory chip is actually erased even after data gain that...
7111208 On-chip standalone self-test system and method  
A method and system are disclosed for providing standalone built-in self-testing of a transceiver chip. The transceiver chip includes packet generators for generating test packets and packet...
7093172 System and method for determining on-chip bit error rate (BER) in a communication system  
A test packet generator ( 225 a ) within a physical layer device ( 230 ) may generate test packets to be communicated over a closed communication path established within the physical layer device (...
7082557 High speed serial interface test  
A high speed, two-way serial interface with a scrambler and de-scrambler may be tested by sending a single word repeatedly through the scrambler to create a pseudo-random sequence. The...
7051252 Ibist identification loopback scheme  
A method and mechanism for testing communication links. A transmitter contact, or transmission point, is assigned a unique identifier. During a given test, the transmitter conveys a test pattern to...
7047459 Method and system for isolation of a fault location in a communications network  
The present invention provides system and method of identifying a failure location in any datapath in a set of datapaths in a communication element, each datapath of the set of datapaths traversing...
7036055 Arrangements for self-measurement of I/O specifications  
Arrangements (circuits, methods, systems) having self-measurement of input/output (I/O) specifications (e.g., input trip-point, output drive-level and pin leakage).
Matches 1 - 50 out of 194 1 2 3 4 >