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7617426 |
Verification method and apparatus
A method for verifying whether a recording/reproducing apparatus properly produces disc management information and records the disc management information on a disc includes preparing a test disc;...
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7613974 |
Fault detection method and apparatus
This invention relates to fault detection in electrical circuits. The invention provides a method and apparatus for testing an input circuit by generating a periodic test signal having a...
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7610526 |
On-chip circuitry for bus validation
Systems, methodologies, media, and other embodiments associated with validating a bus are described. One exemplary system embodiment includes an integrated circuit operably connectable to a bus,...
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7610522 |
Compliance of master-slave modes for low-level debug of serial links
A condition is detected to cause a component having physical layer circuitry with a transmitter and a receiver to enter a testing state. The transmitter transmits a pre-selected data pattern while...
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7603596 |
Memory device capable of detecting its failure
A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for...
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7600162 |
Semiconductor device
A semiconductor device including an interrupt pattern generator for generating an interrupt enabling signal and interrupt data, an input buffer for receiving input serial data, a selector,...
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7599301 |
Communications network tap with heartbeat monitor
A communications network tap, comprises a first terminal and a second terminal adapted to couple the tap in-line in the network and communicate data packets with network devices. A heartbeat...
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7587645 |
Input circuit of semiconductor memory device and test system having the same
An input circuit of a semiconductor memory device includes a data input circuit and a data pattern setting circuit. The data input circuit receives first data, and generates second data by...
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7574633 |
Test apparatus, adjustment method and recording medium
There is provided a test apparatus that tests a device under test including a plurality of data terminals and a clock output terminal, the test apparatus including a plurality of first variable...
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7571365 |
Wafer scale testing using a 2 signal JTAG interface
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2)...
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7559001 |
Method and apparatus for executing commands and generation of automation scripts and test cases
A command execution terminal includes an interactive graphical-user-interface (GUI) for sending commands to devices under test and to capture and display the command responses and maintaining a...
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7549101 |
Clock transferring apparatus, and testing apparatus
There is provided a clock transferring apparatus for synchronizing a pattern signal synchronized with a reference clock with a variable clock based on an oscillation source different from that of...
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7539148 |
Circuit integrity in a packet-switched network
Techniques for performing a continuity check operation include sending a pattern of bits over a packet network connection through a first interface on a packet network to a second interface on the...
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7512854 |
Method and apparatus for testing, characterizing and monitoring a chip interface using a second data path
A data receiver circuit in a receiving chip provides the capability to characterize an interface, which includes one or more inter-chip communication lines, between a transmitting chip and the...
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7506311 |
Test tool for application programming interfaces
Methods and apparatus for enabling the framework and the application code associated with an application programming interface (API) to be efficiently and comprehensively tested are disclosed....
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7506222 |
System for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling
A system for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling includes a slave device and a master device that is coupled to the...
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7500046 |
Abstracted host bus interface for complex high performance ASICs
An interface is provided to couple an input/output device (e.g., a network interface unit) to one or more different host system buses without altering the configuration of the device (e.g., to...
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7493532 |
Methods and structure for optimizing SAS domain link quality and performance
Methods and structures within a SAS domain for automated tuning performance of a coupled pair of transceivers. In one aspect hereof, control registers of a transmitting transceiver coupled to a...
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7490275 |
Method and apparatus for evaluating and optimizing a signaling system
A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive...
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7487423 |
Decoding method, medium, and apparatus
A decoding method, medium, and apparatus capable of preventing error propagation and implementing parallel processing. A decoding method includes comparing encoding information with decoding...
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7480839 |
Qualified anomaly detection
A circuit and method of qualified anomaly detection provides detection and triggering on specific analog anomalies and/or digital data within a qualified area of a serial data stream. A start...
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7478304 |
Apparatus for accelerating through-the-pins LBIST simulation
The present invention provides an apparatus and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a...
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7478298 |
Method and system for backplane testing using generic boundary-scan units
A test system for testing a backplane comprising an adapter assembly and a generic boundary-scan test unit. The adapter assembly includes an application-specific mating connector to communicatively...
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7461308 |
Method for testing semiconductor chips by means of bit masks
A method for testing semiconductor chips is disclosed. In one embodiment, a chip to be tested which has a test logic, at least one test mode is set, the test modes are executed in the chip and test...
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7454676 |
Method for testing semiconductor chips using register sets
A method for testing semiconductor chips having a test logic unit includes: providing a chip having n different register sets, each of which has m different registers that are subdivided into m...
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7447966 |
Hardware verification scripting
Exemplary techniques for verifying a hardware design are described. In a described embodiment, a method comprises compiling an error verification object corresponding to an error verification...
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7447953 |
Lane testing with variable mapping
Memory apparatus and methods selectively map first lanes to second lanes. A memory agent may transfer training and return sequences using different lane mappings. The return sequences may be...
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7444558 |
Programmable measurement mode for a serial point to point link
A serial point to point link that communicatively couples an integrated circuit (IC) device to another IC device is initialized by transferring a training sequence of symbols over the link....
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7437643 |
Automated BIST execution scheme for a link
Training of a link is performed, wherein the link is an interconnect between two devices of a computer system. A built-in self-test (BIST) of the link is performed. A result from the link training...
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7434118 |
Parameterized signal conditioning
A coupling unit is adapted to be coupled between a first and a second unit to be tested. Said coupling unit comprises a first signal path that is adapted to provide a signal connection between at...
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7434114 |
Method of compensating for a byte skew of PCI express and PCI express physical layer receiver for the same
A method of compensating for a byte skew of a PCI Express bus, the method including determining whether received data are in a training sequence or not, setting an alignment point corresponding to...
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7426599 |
Systems and methods for writing data with a FIFO interface
Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed...
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7405723 |
Apparatus for testing display device and method for testing the same
An apparatus for testing a display device includes a display device to display test patterns, a graphic process unit to supply analog mode signals and digital mode signals to the display device,...
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7404115 |
Self-synchronising bit error analyser and circuit
A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator
wherein the generator LFSR generates a first data set which is transmitted through a data bus...
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7404114 |
System and method for balancing delay of signal communication paths through well voltage adjustment
A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of...
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7395466 |
Method and apparatus to adjust voltage for storage location reliability
According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at...
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7386767 |
Programmable bit error rate monitor for serial interface
A programmable bit error rate monitor includes an error counter, a monitoring period counter with a programmable upper bound to set the monitoring period, and an error flag generator that compares...
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7380152 |
Daisy chained multi-device system and operating method
A multi-device system having a daisy chain system bus structure and related method of operation are disclosed. A reference signal having a defined oscillation period is communicated around the...
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7373561 |
Integrated packet bit error rate tester for 10G SERDES
An integrated packet bit error rate tester includes a packet transmit circuit that has a first memory for storing transmit packet data and is connectable to a channel under test. A packet receive...
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7349506 |
Semiconductor integrated circuit and method for testing the same
A method and semiconductor integrated circuit in which a receiver receives reception data and executes reception processing on the basis of a clock signal supplied from a PLL and a transmitter...
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7340655 |
Skew adjustment circuit, skew adjustment method, data synchronization circuit, and data synchronization method
A skew adjustment circuit employs a novel algorithm enabling a reduction in scale of the circuit of a receiver for a Transition Minimized Differential Signaling (T.M.D.S.) link in accordance with...
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7337376 |
Method and system of self-test for a single infrared machine
A system and method of self-test for a single infrared machine. An infrared transimit circuit may be set up succesfully by only using a host with an external infrared module without a use of...
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7331004 |
Data storage system analyzer having self reset
A transmitter board transmits a copy of signals in a system being analyzed by the system analyzer. The copy of such signals comprises serial data in a low byte serial link and in a high byte serial...
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7324392 |
ROM-based memory testing
This invention uniquely partitions the pBIST ROM for storing program and data information. The pBIST unit selectively loads both the algorithm and data, the algorithm only or the data only for each...
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7313753 |
Detector for detecting information carried by a signal having a sawtooth-like shape
A detector for detecting information carried by a signal having a sawtooth-like shape. The detector includes a first band-pass filter with center frequency around a first frequency value for...
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7313738 |
System and method for system-on-chip interconnect verification
A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear...
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7280420 |
Data compression read mode for memory testing
Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data...
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7275198 |
Apparatus and method for transmitting/receiving error detection information in a communication system
Disclosed is an apparatus for generating an error detection information bit sequence for determining a length of data sequence transmitted in a communication system. The apparatus comprises a...
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7275195 |
Programmable built-in self-test circuit for serializer/deserializer circuits and method
A built-in self-test circuit for use in testing a serializer/deserializer circuit includes a programmable transmit register that transmits data to the serializer/deserializer circuit having...
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7274611 |
Method and architecture to calibrate read operations in synchronous flash memory
Architecture to calibrate read operations in non-volatile memory devices. In one embodiment, a synchronous flash memory is disclosed. The synchronous flash memory includes a read sense amplifier, a...
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