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7624312 System, apparatus, computer program product for performing operational validation with limited CPU use of a communications network  
A system, apparatus, computer program product and method of performing operational validation on a system are provided. The system may include a CPU with a cache, a communications network, and a...
7620861 Method and apparatus for testing integrated circuits by employing test vector patterns that satisfy passband requirements imposed by communication channels  
Embodiments of an apparatus and method for high-speed testing of a device under test are described herein, where the device under test is coupled to a tester via a limited passband communication...
7603596 Memory device capable of detecting its failure  
A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for...
7594150 Fault-tolerant architecture of flip-flops for transient pulses and signal delays  
A method and apparatus for a structure of a flip-flop that is tolerant to the noise pulses occurring due to the presence of crosstalk faults by sampling the input data multiple times before and...
7574633 Test apparatus, adjustment method and recording medium  
There is provided a test apparatus that tests a device under test including a plurality of data terminals and a clock output terminal, the test apparatus including a plurality of first variable...
7573967 Input threshold adjustment in a synchronous data sampling circuit  
A data sampler system receives a high-speed data stream and uses a first set of data samplers for sampling the data stream at a first set of clock phase angles to produce a first set of sequential...
7571363 Parametric measurement of high-speed I/O systems  
A phase comparator is used to test a device under test comprising an input/output (I/O) circuit by applying a signal to the device under test; extracting a phase signal from the phase comparator;...
7549095 Error detection enhancement in a microprocessor through the use of a second dependency matrix  
A microprocessor error detection method, includes providing a primary dependency matrix, providing an issue logic for issuing a micro-op, providing a secondary dependency matrix comprising a copy...
7506222 System for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling  
A system for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling includes a slave device and a master device that is coupled to the...
7496813 Communicating simultaneously a functional signal and a diagnostic signal for an integrated circuit using a shared pin  
An integrated circuit 2 including functional circuits 4, 6 and a diagnostic circuit 10 passes a functional signal and a diagnostic signal to/from the integrated circuit using a shared...
7487411 Multi symbol bit detection for SDPSK signals  
This invention discloses a method of accurately detecting the current bit in a SDPSK modulated signal at the receiver. The proposed method calculates the current bit from the past-detected bits and...
7480839 Qualified anomaly detection  
A circuit and method of qualified anomaly detection provides detection and triggering on specific analog anomalies and/or digital data within a qualified area of a serial data stream. A start...
7469367 Phase error determination method and digital phase-locked loop system  
In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The...
7463695 System for five-level non-causal channel equalization  
A system and method are provided for five-level non-causal channel equalization in a communications system. The method comprises: receiving a non-return to zero (NRZ) data stream input;...
7461317 System and method for aligning a quadrature encoder and establishing a decoder processing speed  
A system and method are disclosed for determining the minimum required processing speed for a quadrature decoder using measurements of encoder performance, and to assess the safety factor of a...
7461308 Method for testing semiconductor chips by means of bit masks  
A method for testing semiconductor chips is disclosed. In one embodiment, a chip to be tested which has a test logic, at least one test mode is set, the test modes are executed in the chip and test...
7454676 Method for testing semiconductor chips using register sets  
A method for testing semiconductor chips having a test logic unit includes: providing a chip having n different register sets, each of which has m different registers that are subdivided into m...
7434114 Method of compensating for a byte skew of PCI express and PCI express physical layer receiver for the same  
A method of compensating for a byte skew of a PCI Express bus, the method including determining whether received data are in a training sequence or not, setting an alignment point corresponding to...
7424656 Clocking methodology for at-speed testing of scan circuits with synchronous clocks  
A clocking method for at-speed scan testing for delay defects in cross-domain paths of interacting synchronous clock domains in a scan circuit, each path originating from a source memory element in...
7424651 Method and apparatus for decision threshold control in an optical signal receiver  
An apparatus and method for decision threshold control in an optical signal receiver. A forward error correction (FEC) decoder provides a feedback signal representative of corrected errors. The...
7424230 Digital transmission system  
This digital transmission system is provided with a transmitting apparatus that transmits digital data signals and a receiving apparatus that receives the digital data signals transmitted over a...
7404115 Self-synchronising bit error analyser and circuit  
A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus...
7395475 Circuit and method for fuse disposing in a semiconductor memory device  
A fuse disposing circuit executes a same test as in a state before a fuse is cut, even in case the fuse is cut. For this, the fuse disposing circuit in accordance with the invention includes a test...
7392441 Method of performing operational validation with limited CPU use of a communications network  
A system, apparatus, computer program product and method of performing operational validation on a system are provided. The system may include a CPU with a cache, a communications network, and a...
7392440 Optical reception device and optical reception method  
An optical signal receiving equipment including an optical-electrical converter configured to convert optical signals into electronic signals; first deciders configured to transform the electronic...
7389455 Register file initialization to prevent unknown outputs during test  
A system and method for initializing a register file during a test period for an integrated circuit, wherein the register file has one or more input ports. A counter, when enabled, is initialized...
7373577 CAN system  
Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller...
7370247 Dynamic offset compensation based on false transitions  
A method and apparatus provide a receiver with an architecture to regulate a bit error rate of the receiver using an offset based on detecting false transitions in received data. In an embodiment,...
7363553 System and method for adjusting soft decision thresholds in a soft-decision error correction system  
The soft decision thresholds in a soft decision forward error correction (FEC) system may be adjusted based on mutual information of a detected signal. In one embodiment, a recursive algorithm may...
7346824 Match circuit for performing pattern recognition in a performance counter  
A match circuit connected to a bus carrying data is described. In one embodiment, the match circuit comprises logic for activating a match_mm signal when a selected N-bit portion of the data...
7321948 Highly available system test mechanism  
Boards in a system are interconnected by a first set of signals including a first control signal and first function signals. Each board in the system includes a second set of signals corresponding...
7313738 System and method for system-on-chip interconnect verification  
A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear...
7281176 Determining signal quality and selecting a slice level via a forbidden zone  
In one embodiment, a method may determine a number of data transitions occurring in a forbidden zone at each of a first and second slice levels and adjust a slice level offset for an amplifier...
7260755 Skewed inverter delay line for use in measuring critical paths in an integrated circuit  
An integrated circuit includes a testable delay path. A transition of a delay path input signal causes a subsequent transition of a delay path output signal. A pulse generator receives the delay...
7254345 Receiver and receiving method capable of detecting an eye aperture size formed by reception data signals  
In a receiver operable in response to a data signal, an eye aperture size is detected along a time axis by an eye aperture detection circuit and is controlled by a control circuit so that it...
7249293 Method and device for testing for the occurrence of bit errors  
In a method and a device for testing a plurality of measured devices in parallel by using a single signal generator and a single bit error measuring device, a serial testing signal for is converted...
7216267 Systems and methods for multistage signal detection in mimo transmissions and iterative detection of precoded OFDM  
Systems and methods for multi-stage signal detection in MIMO transmission including Bernoulli-Gaussian detection are provided. A multistage iterative signal decoder is provided that exploits the...
7149938 Non-causal channel equalization  
A system and method are provided for non-causal channel equalization in a communications system. The method comprises: establishing three thresholds; receiving a binary serial data stream;...
7117401 Method and apparatus for optimizing timing for a multi-drop bus  
A first device delivers a clock offset message to a second device. The second device offsets its data transmission according to the clock offset message. A test pattern is transmitted from the...
7107499 System and method for adjusting a non-return to zero data stream input threshold  
A state machine method and system are provided for determining non-causal channel equalization thresholds. The method comprises: receiving a non-return to zero (NRZ) data stream encoded with...
7085970 Fast detection of incorrect sampling in an oversampling clock and data recovery system  
A method, in an oversampling clock and data recovery system, for detecting that sampling is stuck taking place at a data edge, by detecting a data edge in an early or a late region relative to a...
7080295 Methods and systems for detecting symbol erasures  
A technique for determining a symbol erasure threshold for a received communication signal containing symbol information is disclosed. The technique begins by performing a first threshold...
7076419 Using sign extension to compress on-chip data processor trace and timing information for export  
An emulation parameter indicative of a data processing operation performed by a data processor is exported from the data processor. The parameter value is provided as a plurality of digital bits....
7065685 Method for non-causal channel equalization  
A system and method are provided for non-causal channel equalization in a communications system. The method comprises: establishing a first threshold (V 1 ) to distinguish a high probability...
7039855 Decision function generator for a Viterbi decoder  
A decision function generator for a Viterbi decoder includes a compressor module for receiving arguments of a decision function and for evaluating functions of the arguments of the decision...
7036053 Two dimensional data eye centering for source synchronous data transfers  
A method for optimizing a source synchronous clock reference signal timing to capture data from a memory device (e.g., DDR SDRAM) includes conducting an iterative two-dimensional data eye search...
7024599 System and method for non-causal channel equalization  
A system and method are provided for non-causal channel equalization in a communications system. The method comprises: receiving a non-return to zero (NRZ) data stream input; establishing...
6990615 Data processing device  
A data and clock recovery circuit is provided for generating a recovered version of a transmitted data stream. The data and clock recovery circuit comprises three main circuit modules, namely a...
6981204 Programmable glitch filter for an asynchronous data communication interface  
An apparatus and a method for filtering glitches in a data communications controller receiving asynchronous input data signals varying between two signal levels representing two bit values and...
6981185 Methods and apparatus to correct duty cycle  
An apparatus for correcting duty cycle error is provided which includes circuitry capable of determining existence of a duty cycle error from input data received over data transmissions lines where...
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