|
Match
|
Document |
Document Title |
|
|
7617426 |
Verification method and apparatus
A method for verifying whether a recording/reproducing apparatus properly produces disc management information and records the disc management information on a disc includes preparing a test disc;...
|
|
|
7613974 |
Fault detection method and apparatus
This invention relates to fault detection in electrical circuits. The invention provides a method and apparatus for testing an input circuit by generating a periodic test signal having a...
|
|
|
7603596 |
Memory device capable of detecting its failure
A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for...
|
|
|
7603266 |
Generic emulator of devices in a device communications protocol
The generic device emulator provides an operational emulation of the behavior of any desired device within a device connectivity or other communications protocol as specified in a description of...
|
|
|
7599301 |
Communications network tap with heartbeat monitor
A communications network tap, comprises a first terminal and a second terminal adapted to couple the tap in-line in the network and communicate data packets with network devices. A heartbeat...
|
|
|
7587645 |
Input circuit of semiconductor memory device and test system having the same
An input circuit of a semiconductor memory device includes a data input circuit and a data pattern setting circuit. The data input circuit receives first data, and generates second data by...
|
|
|
7587463 |
Apparatus and method of rewriting firmware
A main controller sends a “rewrite mode” command to an engine controller. Receiving the command, the engine controller 12 sends a “roger” status. This switches the mode from a print mode...
|
|
|
7565587 |
Background block erase check for flash memories
Memory devices and methods of operating memory devices provide for using differing potentials during erase verify operations facilitate normal erase operations and subsequent erase check...
|
|
|
7552367 |
Fault recording and sequence of events recording device capable of recording communication-based signals related to electrical power systems
A method for recording analog signals and digitally encoded information associated with primary and secondary devices of an electric power system includes: receiving a plurality of analog output...
|
|
|
7519873 |
Methods and apparatus for interfacing between test system and memory
Methods and apparatuses for entering at least one memory into a test mode are provided. At least one test MRS bit may be stored in a first register for controlling the memory. At least one test MRS...
|
|
|
7516376 |
Test pattern generator, test circuit tester, test pattern generating method, test circuit testing method, and computer product
A test circuit tester includes a scan-chain input-output information generator that generates information for an input and an output of the scan chain that is scan-chain input-output information,...
|
|
|
7506311 |
Test tool for application programming interfaces
Methods and apparatus for enabling the framework and the application code associated with an application programming interface (API) to be efficiently and comprehensively tested are disclosed....
|
|
|
7500170 |
Method and apparatus for error detection in a data block
A transmitting device generates a data block including a first field having a first plurality of bits that includes an error detection portion and a second field having a second plurality of bits;...
|
|
|
7500161 |
Correcting test system calibration and transforming device measurements when using multiple test fixtures
A test system and methods using the test system correlate measurements of a device under test (DUT) regardless of which test fixture is used for in-fixture testing of the DUT. The test system...
|
|
|
7484160 |
Systems and methods for delineating a cell in a communications network
A method of performing cell delineation in a communications network is described. The method includes providing a data cell defined based on a communications protocol. The data cell forms at least...
|
|
|
7478304 |
Apparatus for accelerating through-the-pins LBIST simulation
The present invention provides an apparatus and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a...
|
|
|
7461317 |
System and method for aligning a quadrature encoder and establishing a decoder processing speed
A system and method are disclosed for determining the minimum required processing speed for a quadrature decoder using measurements of encoder performance, and to assess the safety factor of a...
|
|
|
7437644 |
Automatic self-testing of an internal device in a closed system
A closed system such as a TET system in which self-testing of all components of the implantable medical device whose malfunction could negatively impact on the proper operation of the closed system...
|
|
|
7428674 |
Monitoring the state vector of a test access port
Monitoring of the state vector of a test access port (TAP) permits isolation of the root cause of improper transitions of the state vector due to various factors, including electrical noise. The...
|
|
|
7412620 |
Method for testing ability to recover from cache directory errors
A method, apparatus, and computer program product are disclosed for testing a data processing system's ability to recover from cache directory errors. A directory entry is stored into a cache...
|
|
|
7409620 |
Simplified high speed test system
A method for configuring a testing system that includes a step of connecting a commercially available computer (CACMP) for directly controlling transmission of a plurality of test vectors to a test...
|
|
|
7406628 |
Simulated error injection system in target device for testing host system
A method and device are provided that use a sequencer in the device to control interactions on an interface bus. The sequencer is programmed to interrupt a co-processor before execution of a...
|
|
|
7401269 |
Systems and methods for scripting data errors to facilitate verification of error detection or correction code functionality
In one embodiment, the present invention is directed to a method for inserting errors into data to facilitate validation of an error detection algorithm. The method comprises: receiving a data...
|
|
|
7395479 |
Over-voltage test for automatic test equipment
Automatic test equipment including a digital test instrument that may test for and respond to over-voltage conditions. Information on over-voltage conditions may be used in detecting or diagnosing...
|
|
|
7395475 |
Circuit and method for fuse disposing in a semiconductor memory device
A fuse disposing circuit executes a same test as in a state before a fuse is cut, even in case the fuse is cut. For this, the fuse disposing circuit in accordance with the invention includes a test...
|
|
|
7392438 |
Automatic safety test system
An automatic safety test system, which comprises a control interface of a control unit for controlling the switching of a switch in a server unit and automatically switching to a specified testing...
|
|
|
7373577 |
CAN system
Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller...
|
|
|
7366971 |
Semiconductor memory having sub-party cell array error correction
Disposed on both sides of a parity cell array are a first regular cell array and a sub parity generation circuit therefor, and a second regular cell array and a sub parity generation circuit...
|
|
|
7349506 |
Semiconductor integrated circuit and method for testing the same
A method and semiconductor integrated circuit in which a receiver receives reception data and executes reception processing on the basis of a clock signal supplied from a PLL and a transmitter...
|
|
|
7340655 |
Skew adjustment circuit, skew adjustment method, data synchronization circuit, and data synchronization method
A skew adjustment circuit employs a novel algorithm enabling a reduction in scale of the circuit of a receiver for a Transition Minimized Differential Signaling (T.M.D.S.) link in accordance with...
|
|
|
7325173 |
Semiconductor memory having error correction
During a first data compression test mode which disables an error correction function, first test data are written to a first regular memory block. Second test data are written to not only a second...
|
|
|
7324982 |
Method and apparatus for automated debug and optimization of in-circuit tests
A method and apparatus for automatically debugging and optimizing an in-circuit test that is used to test a device under test on an automated tester is presented. The novel test debug and...
|
|
|
7321996 |
Digital data error insertion methods and apparatus
Methods and apparatus are provided to insert errors into digital data. The errors can be inserted into the data itself, or into the corresponding error correcting code bits. The invention comprises...
|
|
|
7318000 |
Biometric quality control process
Systems and methods configured to guide and manage laboratory analytical process control operations. A Biometric quality control (QC) process application is configured to monitor bias and...
|
|
|
7296212 |
Multi-dimensional irregular array codes and methods for forward error correction, and apparatuses and systems employing such codes and methods
Methods, apparatuses, and systems for encoding information symbols comprising loading information symbols into a data array with n (1) rows and n (2) columns, wherein each column has k i (1) ...
|
|
|
7293206 |
Test data pattern for testing a CRC algorithm
A method of generating a test data pattern for testing a CRC algorithm, the CRC algorithm configured to generate CRC values based on a generator polynomial, the method including identifying a...
|
|
|
7290197 |
Correcting data using redundancy blocks
Errors in data retrieved from a storage medium are corrected by retrieving a plurality of data blocks and a plurality of redundancy blocks associated with the plurality of data blocks from the...
|
|
|
7281184 |
Test system and method for testing a circuit
A test-device for testing an electric circuit comprises a data stream generator for generating a first data stream to be fed to an electric circuit which generates a second data stream in response...
|
|
|
7278084 |
Method and system for providing communications security
Generating a protected content stream from a data stream provides enhanced security in short-range wireless communications networks. This protected content stream is transmitted across a first...
|
|
|
7278076 |
System and scanout circuits with error resilience circuit
In one embodiment, an apparatus is provided with a system circuit, a scanout circuit and an error detecting circuit. The system circuit is adapted to generate a first output signal in response to a...
|
|
|
7266735 |
Semiconductor device having ECC circuit
A semiconductor device in which at least one bit of data bits configuring data read out from a memory is supplied to a pseudo error generating circuit in a test mode to generate a pseudo error bit...
|
|
|
7254753 |
Circuit and method for configuring CAM array margin test and operation
A test circuit for a content addressable memory (CAM) match detection circuit that permits testing of the margin of the match detection circuit. By applying various loads to the matchline and/or...
|
|
|
7249306 |
System and method for generating 128-bit cyclic redundancy check values with 32-bit granularity
A System and Method for generating Cyclic Redundancy Check (CRC) values in a system adapted simultaneously handling a plurality of blocks in parallel is described. Included is a memory or other...
|
|
|
7249302 |
Integrated test-on-chip system and method and apparatus for manufacturing and operating same
A microchip system comprises a self check subsystem operable to perform a self test of at least one subsystem of the microchip system, and/or on the interoperability of subsystems. An antenna and a...
|
|
|
7249284 |
Complex system serviceability design evaluation method and apparatus
A technique is provided for designing and evaluating service models for components, functions, subsystems and field replaceable units in a complex machine system. At a component or item level, each...
|
|
|
7218670 |
Method of measuring the performance of a transceiver in a programmable logic device
The performance of a serial data transceiver in a programmable logic device may be determined by applying a stress sequence of sequential data to a receiver of the transceiver, comparing the...
|
|
|
7137045 |
Decoding method and apparatus therefor
A decoding method and an apparatus operate by performing error correction on code words of an error correcting code block in one direction selected from a row direction and a column direction,...
|
|
|
7134056 |
High-speed chip-to-chip communication interface with signal trace routing and phase offset detection
A high-speed parallel interface for communicating data between integrated circuits is disclosed. In one embodiment, the transmitter controller accepts 40-bit wide data every 167 Mhz clock cycle,...
|
|
|
7127646 |
System and method for generating real time errors for device testing
Test circuitry for supporting real-time testing of data exception software may be included on an integrated circuit. The circuitry supports the identification of a data unit or data group other...
|
|
|
7111198 |
Multithread auto test method
A multithread auto test method is disclosed for the test process of computer hardware. According to the exclusion relation among the unique IDs of the test items, a multithread executable logic is...
|