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7624323 |
Method and apparatus for testing an IC device based on relative timing of test signals
An apparatus for testing an IC device includes a test signal generator for generating a predefined sequence of test signals that are input to the IC device. A timing skew monitor is provided for...
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7624311 |
Method and apparatus for converting interface between high speed data having various capacities
Provided are a method and an apparatus for converting an interface between high speed data having various capacities. The apparatus includes a data transmitting part and a data receiving part. The...
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7624310 |
System and method for initializing a memory system, and memory device and processor-based system using same
Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read...
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7620857 |
Controllable delay device
Two delay chains having in each case n series-connected unidirectional delay elements are provided for controllably delaying electrical signals between a circuit input and at least one circuit...
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7617431 |
Method and apparatus for analyzing delay defect
The apparatus for analyzing a delay defect of the present invention obtains the RC of the maximal incidence among region codes (RCs) to which check circuits detecting errors caused with gradual...
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7600162 |
Semiconductor device
A semiconductor device including an interrupt pattern generator for generating an interrupt enabling signal and interrupt data, an input buffer for receiving input serial data, a selector,...
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7596173 |
Test apparatus, clock generator and electronic device
There is provided a clock generator for generating a single-phase clock into which jitter has been injected, having a multi-phase clock generating section for generating a plurality of clock...
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7594150 |
Fault-tolerant architecture of flip-flops for transient pulses and signal delays
A method and apparatus for a structure of a flip-flop that is tolerant to the noise pulses occurring due to the presence of crosstalk faults by sampling the input data multiple times before and...
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7594146 |
Apparatus, method, and program for correcting time of event trace data
A time correcting apparatus includes a data input section which inputs all event trace data generated for each event executed on computing devices and outputs the event trace data in order of...
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7587650 |
Clock jitter detector
A detector to detect the magnitude of the jitter that may occur in a first clock signal and a second clock signal and to generate an alarm signal if the magnitude of the jitter exceeds the...
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7587640 |
Method and apparatus for monitoring and compensating for skew on a high speed parallel bus
Methods and apparatus are provided for monitoring and compensating for skew on a high speed parallel bus. Delay skew for a plurality of signals on a parallel bus is monitored by obtaining a...
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7574633 |
Test apparatus, adjustment method and recording medium
There is provided a test apparatus that tests a device under test including a plurality of data terminals and a clock output terminal, the test apparatus including a plurality of first variable...
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7574632 |
Strobe technique for time stamping a digital signal
A system and apparatus generates a time-stamp to identify and record the time of an event such as an edge received in a data signal or clock signal. A set of strobe pulses can be generated by...
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7571407 |
Semiconductor integrated circuit and method of testing delay thereof
A semiconductor integrated circuit comprises: a first area, formed on a semiconductor chip, which operates at a first predetermined voltage and a first predetermined frequency; a second area,...
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7571359 |
Clock distribution circuits and methods of operating same that use multiple clock circuits connected by phase detector circuits to generate and synchronize local clock signals
Multiple clock circuits are connected by phase detector circuits to generate and synchronize local clock signals. For example, a clock distribution circuit includes a first clock circuit that is...
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7565582 |
Circuit for testing the AC timing of an external input/output terminal of a semiconductor integrated circuit
In a semiconductor integrated circuit, one of two signals generated from a first logic circuit is delayed in a first delay addition circuit, looped back by an input/output terminal, and then...
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7562266 |
Method and device for verifying timing in a semiconductor integrated circuit
A timing verification device for performing effective timing verification while correctly taking variation into account. The timing verification device receives a technology file and extracts a...
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7558995 |
Method and apparatus for eliminating noise induced errors during test of a programmable logic device
A method and apparatus for substantially eliminating noise induced errors caused by a premature start-up sequence between configuration of an integrated circuit (IC) and execution of functional...
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7558991 |
Device and method for measuring jitter
A test device contains a data pattern generator for providing a delta-sigma-modulated data stream sampled with a sampling frequency f s at its output. A phase modulator generates a test clock...
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7558336 |
Semiconductor device, memory device and memory module having digital interface
An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically...
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7557561 |
Electronic device, circuit and test apparatus
There is provided an electronic device for receiving an input data signal and an input clock signal that indicates a timing to obtain the input data signal. The electronic device includes a first...
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7552366 |
Jitter tolerance testing apparatus, systems, and methods
Apparatus, systems, methods, and articles may operate to move an output phase of a clock phase adjustment device associated with a master clock through a plurality of phase shifts relative to a...
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7549108 |
Methods and systems for secure control of system modes and sub-modes
Systems, methods and data structures are provided for representing robust data transmitted within a control system. The data structure includes at least two data fields identifying sub-modules and...
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7549092 |
Output controller with test unit
There is provided an output controller with a test unit, which can test an appropriate delay amount according to an operating frequency under a real situation. The output controller includes an...
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7546494 |
Skew-correcting apparatus using dual loopback
An apparatus for determining the amount of skew injected into a high-speed data communications system, including a plurality of lanes having a data bus per lane, relative to a reference lane, for...
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7543209 |
Characterizing jitter sensitivity of a serializer/deserializer circuit
Disclosed herein is an improved serializer/deserializer (SERDES) circuit ( 102 ) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization...
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7543202 |
Test apparatus, adjustment apparatus, adjustment method and adjustment program
A test apparatus that test a device under test includes a plurality of signal input/output units each of which has a signal output section and a signal input section that: firstly, adjusts each of...
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7543196 |
Apparatus for testing integrated circuit
An apparatus for testing integrated circuits is disclosed. The apparatus for testing integrated circuits comprises an integrated circuit and a tester. The integrated circuit undergoing testing...
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7536610 |
Method for detecting resistive-open defects in semiconductor memories
The present invention relates to a method for detecting delay faults in a semiconductor memory. In an example embodiment, address bits and data bits are generated according to a test pattern...
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7536579 |
Skew-correcting apparatus using iterative approach
An apparatus for determining the amount of skew to be injected for system skew compensation in a high-speed data communications system including a plurality of lanes with a data bus per lane. Such...
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7533317 |
Serializer/deserializer circuit for jitter sensitivity characterization
Disclosed herein is an improved serializer/deserializer (SERDES) circuit ( 102 ) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization...
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7526701 |
Method and apparatus for measuring group delay of a device under test
A method of measuring group delay of a device under test is provided. The method includes the steps of providing an analog input signal with a predetermined period to the device under test to...
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7523379 |
Method for time-delayed data protection
A method is provided for time-delayed data protection. During a writing operation, data is written to a register file, an error correction code is computed, and a delayed write of the error...
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7516379 |
Circuit and method for comparing circuit performance between functional and AC scan testing in an integrated circuit (IC)
A circuit and method for determining operating speed of a clock associated with an integrated circuit (IC), includes an IC logic element, a scan chain, and a calibration circuit including a first...
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7516374 |
Testing circuit and related method of injecting a time jitter
A testing method includes selecting a low-pass filter by simulation, generating testing signals with the low-pass filter receiving output signals of an under-test circuit, and outputting the...
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7506228 |
Measuring the internal clock speed of an integrated circuit
A system and methods to transfer data between a testing interface and an IC. The system may include a synchronization subsystem to monitor the transitions of the test interface clock and/or IC...
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7506222 |
System for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling
A system for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling includes a slave device and a master device that is coupled to the...
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7502974 |
Method and apparatus for determining which timing sets to pre-load into the pin electronics of a circuit test system, and for pre-loading or storing said timing sets
In one embodiment, a method includes, providing a test program designed to control a circuit test system. The circuit test system has a plurality of test channels, each test channel of which is...
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7500156 |
Method and apparatus for verifying multi-channel data
A multi-channel data verifying apparatus and method are provided. The apparatus includes a receiver receiving N data channels and a deskew channel generated by sequentially extracting a...
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7500155 |
Average time extraction circuit for eliminating clock skew
The method involves detecting a first signal characterized by a periodically occurring first event, detecting a second signal characterized by a periodically occurring second event, and based on...
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7496803 |
Method and apparatus for testing an integrated device's input/output (I/O)
A plurality of timing diagrams and different versions of circuits to test an integrated device in a test mode of operation. The invention allows for pulling in a strobe and eliminating the need for...
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7495465 |
PVT variation detection and compensation circuit
A compensation circuit and a method that compensates for process, voltage and temperature (PVT) variations in an integrated circuit that includes functional modules. The compensation circuit...
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7490273 |
Auto-calibration method for delay circuit
An auto-calibration method is applied to a delay circuit, which includes a plurality of delay chains. If the number of accumulative errors of a designated delay chain as a current delay path is...
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7484166 |
Semiconductor integrated circuit verification method and test pattern preparation method
In the inventive semiconductor integrated circuit verification method, based upon expected values of a signal from an integrated circuit, which are obtained by RTL verification or the like, and...
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7484135 |
Semiconductor device having a mode of functional test
A semiconductor device includes a circuit block; a first signal path for guiding a test signal to a signal input terminal of the circuit block; a second signal path for guiding a test clock to a...
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7480882 |
Measuring and predicting VLSI chip reliability and failure
This embodiment replaces the use of LBIST to get a pass or no-pass result. A selective signature feature is used to collect the top failing paths, by shmooing the chip over a cycle time. These...
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7480838 |
Method, system and apparatus for detecting and recovering from timing errors
Methods and systems to facilitate an efficient circuit for detecting internal timing errors for integrated devices, including a hierarchy of reporting the detection of the timing error from a...
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7478287 |
Semiconductor integrated circuit and electronic device
A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a...
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7475297 |
Efficient method for computing clock skew without pessimism
The present invention includes a method and an apparatus, in one embodiment, in the form of an integrated circuit and programmable fabric design tool, for calculating skew in a manner that does not...
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7472319 |
Remote control signal receiver and remote control signal receiving method
A remote control signal receiver receives a remote control signal in which bit signals are included as pulse signals. The remote control signal receiver includes a remote control signal receiving...
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