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7404110 Method and system for self-assembling instruction opcodes for a custom random functional test of a microprocessor  
In one embodiment, a method may include generating a test code segment including a number of selected opcodes and executing the test code segment for a plurality of iterations. The method may also...
7404109 Systems and methods for adaptively compressing test data  
Systems and methods for adaptively compressing test data are disclosed. One such method comprises the steps of examining a test data file that includes a first plurality of data units corresponding...
7401273 Recovery from errors in a data processing apparatus  
A data processing apparatus and method are provided for recovering from errors in the data processing apparatus. The data processing apparatus comprises processing logic operable to perform a data...
7400555 Built in self test circuit for measuring total timing uncertainty in a digital data path  
A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and...
7397289 Skew adjusting method, skew adjusting apparatus, and test apparatus  
There is provided a skew adjusting apparatus for adjusting a skew between a positive-side differential signal and a negative-side differential signal in differential signals inputted from an...
7389449 Edge selecting triggering circuit  
A triggering circuit asserts a trigger signal in response to edges of a digital signal conveying a repetitive pattern of edges. The triggering circuit generates first data having a value...
7373560 Circuit for measuring signal delays of asynchronous inputs of synchronous elements  
A system measures propagation delays in any number of test circuits, each having two asynchronous inputs and an output, without using their clock inputs to re-initialize the test circuits during...
7370245 Cross-correlation of delay line characteristics  
Cross-correlation of delay line characteristics is described. An integrated circuit for cross-correlation testing includes: a first ring oscillator and a second ring oscillator. The first ring...
7369623 Apparatuses to simultaneously distribute clock signals and data on integrated circuits, interposers, and circuit boards  
A technique is described for simultaneously and synchronously transmitting digital data and a clock signal in a digital integrated circuit, circuit board, or system. The technique is based on the...
7363551 Systems and methods for measuring signal propagation delay between circuits  
Embodiments include systems and methods for measurement of signal propagation delay between Input/Output (IO) Loopback (IOLB) circuits. Embodiments include measurement of an output delay time of a...
7360128 Method of testing memory device  
A test method of a memory device equipped with an internal signal generating circuit which generates an internal signal with a fixed cycle asynchronous with a signal from the outside is disclosed...
7360127 Method and apparatus for evaluating and optimizing a signaling system  
A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive...
7359407 Data interface that is configurable into separate modes of operation for sub-bit de-skewing of parallel-fed data signals  
A data interface is provided that can de-skew data signals by taking into account different skewing effects on each data signal. The data interface can be used, for example, in a communication...
7355421 Semiconductor apparatus testing arrangement and semiconductor apparatus testing method  
A semiconductor apparatus testing arrangement for testing a plurality of semiconductor devices produced on a semiconductor substrate, has a substrate on which a plurality of testing units are...
7353420 Circuit and method for generating programmable clock signals with minimum skew  
A programmable clock deskewer generates an output clock with minimal clock skew. This is accomplished by means of a single series path coupling the input clock to the output clock. The programmable...
7340655 Skew adjustment circuit, skew adjustment method, data synchronization circuit, and data synchronization method  
A skew adjustment circuit employs a novel algorithm enabling a reduction in scale of the circuit of a receiver for a Transition Minimized Differential Signaling (T.M.D.S.) link in accordance with...
7334168 Semiconductor integrated circuit which properly executes an operational test of a circuit under test in the semiconductor integrated circuit  
A semiconductor integrated circuit includes a circuit under test coupled to the logic circuit to receive a plurality internal test signals and a delay time measurement terminal from which a delay...
7331005 Semiconductor circuit device and a system for testing a semiconductor apparatus  
Methods and apparatus for testing a semiconductor device. A testing interface is configured to interface with an external test apparatus and a device under test (DUT). In one embodiment, the...
7330489 Distributed data synchronization apparatus and method  
Disclosed is a method and apparatus for synchronizing data in a number of separate integrated circuits. In one embodiment, the apparatus includes a first integrated circuit configured to receive...
7325172 Failsafe RLC reset method for a wireless communication system  
Embodiments of the present invention relate to a method. The method includes synchronizing a first device and a second device. If the first device and the second device both initiate the...
7324983 Reproducible selection of members in a hierarchy  
A method for selecting members in a hierarchy includes determining a sequence of one or more actions associated with a member selection tree. The actions collectively selecting one or more members...
7305603 Boundary scan cell and methods for integrating and operating the same  
An apparatus for performing a boundary scan test is provided, along with method for integrating and operating the same. The apparatus includes an asynchronous flip-flop that has a data input, a...
7302633 LSI design system, logic correction support equipment, logic correction support method used therefor, and program therefor  
Logic correction support equipment supports logic correction of a logic circuit in LSI design for synthesizing a logic circuit from a register transfer level by logic synthesis. The logic...
7299386 Apparatus and method for detecting address characteristics for use with a trigger generation unit in a target processor  
A comparator unit includes first and second comparator components. The first and second comparator components exchange signals and generate signals when certain characteristics are met. The...
7296195 Bit synchronization for high-speed serial device testing  
An apparatus for testing electronic devices employs a programmable device to adjust the timing of the strobes such that the strobes sample the bit stream from a device under test at or near the...
7296104 Automated calibration of I/O over a multi-variable eye window  
A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a...
7290183 Method of testing semiconductor apparatus  
A method of testing a semiconductor apparatus includes a step of dividing a region in the semiconductor apparatus into a plurality of divided regions, a step of extracting all of paths starting at...
7287200 Jitter applying circuit and test apparatus  
There is provided a jitter application circuit for generating a clock signal containing a phase jitter component corresponding to given jitter data, having a PLL circuit for generating an...
7278069 Data transmission apparatus for high-speed transmission of digital data and method for automatic skew calibration  
A data transmission apparatus and method employing the phase noise characteristics within the receiving registers to measure and control the characteristics of the channel as a function of the data...
7272679 Protocol independent data transmission using a 10 Gigabit Attachment Unit interface  
Transmitting data across a scalable, flexible speed, serial bus in a communication protocol independent manner.
7265590 Semiconductor apparatus for monitoring critical path delay characteristics of a target circuit  
A semiconductor apparatus for flexibly and effectively configuring a delay monitor circuit without an increase in circuit scale includes a delay signal generation circuit for switching the...
7260755 Skewed inverter delay line for use in measuring critical paths in an integrated circuit  
An integrated circuit includes a testable delay path. A transition of a delay path input signal causes a subsequent transition of a delay path output signal. A pulse generator receives the delay...
7251765 Semiconductor integrated circuit and method for testing a semiconductor integrated circuit  
A semiconductor integrated circuit includes a first delay circuit generating a first delay clock; a second delay circuit generating a second delay clock; a first register registering a value of a...
7249306 System and method for generating 128-bit cyclic redundancy check values with 32-bit granularity  
A System and Method for generating Cyclic Redundancy Check (CRC) values in a system adapted simultaneously handling a plurality of blocks in parallel is described. Included is a memory or other...
7249290 Deskew circuit and disk array control device using the deskew circuit, and deskew method  
A deskew circuit includes, for clock and every bit of data, a variable delay circuit between a receiver that receives data and a flip-flop that first latches the data, in which a detecting pattern...
7246286 Testing methods and chips for preventing asnchronous sampling errors  
Testing methods and chips preventing sampling errors caused by asynchronous effect. The chip comprises a first logic portion driven by a first clock signal with a first operating frequency, and a...
7245686 Fast skew detector  
Signal processing apparatus, including a circuit which processes signals received on multiple channels so as to extract therefrom at least first and second sequences of symbols, and a FIFO, which...
7243272 Testing of integrated circuit receivers  
A method for testing a data recovery circuit (DRC) includes disturbing a running variable in a closed control loop of the DRC, as the DRC is processing a received test signal. Data recovered by the...
7240249 Circuit for bit skew suppression in high speed multichannel data transmission  
A deskewing circuit configured to receive a main clock signal wherein data bits are misaligned with respect to the main clock signal. A multiphase clock generator coupled to the main clock to...
7240248 Apparatus and method for reducing false triggering of a signal due to an electrostatic discharge event  
An apparatus and method for reducing false triggering of a signal due to an electrostatic discharge event are disclosed. The method includes detecting a high voltage on a signal received at an...
7236555 Method and apparatus for measuring jitter  
In a method for measuring jitter, a signal under test is inputted to generate signal transition locations. A signal transition location is latched using a sampling clock signal, and the signal...
7233599 Interface device with stored data on transmission lines characteristics  
The present invention relates to high speed communications, in particular, to an interface device between a transmitting device and a receiving device of a transmission system, wherein the...
7231453 Temporal drift correction  
Temporal drift correction may be provided in a real-time audio communication system by measuring a size of a receiving data buffer and comparing that size to a predetermined nominal data buffer...
7228466 Method of detecting violation of block boundary and apparatus therefor  
A disk recording apparatus and method therefore including a boundary violation detector to determine whether a violation of a block boundary occurs on a disk by determining a phase difference...
7228464 PICA system timing measurement and calibration  
PICA probe system apparatus is described, including apparatus for calibrating an event timer having a coarse measurement capability in which time intervals defined by clock boundaries are counted...
7225370 Eye width characterization mechanism  
An eye width characterization mechanism determines a pass setting of a sampling phase positioned within an eye width of received data. The sampling phase is incremented in a first direction from...
7225354 Circuit and method for aligning transmitted data by adjusting transmission timing for a plurality of lanes  
A circuit and a method for aligning transmitted data by adjusting transmission timing for a plurality of lanes. The method includes utilizing different initial values to reset a count value...
7219270 Device and method for using a lessened load to measure signal skew at the output of an integrated circuit  
A device and method are provided for testing the timing of an output signal from a circuit. The output signal can be sent from a circuit contained within a portion of an integrated circuit, and...
7219269 Self-calibrating strobe signal generator  
A self-calibrating strobe signal generator for a BIST circuit responds to an edge of an input strobe signal by generating corresponding edges of first and second strobe signals separated in time by...
7210082 Method for performing ATPG and fault simulation in a scan-based integrated circuit  
A method for performing ATPG (automatic test pattern generation) and fault simulation in a scan-based integrated circuit, based on a selected clock order in a selected capture operation, in a...
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