Matches 251 - 300 out of 390 < 1 2 3 4 5 6 7 8 >
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5768283 Digital phase adjustment circuit for asynchronous transfer mode and like data formats  
A digital phase adjustment circuit adjusts the phase between cell signals and a start-of-cell marker. The circuit relies on a known data pattern in unassigned cell signals in order to determine the...
5748672 System for measuring jitter in a non-binary digital signal  
To measure various frequency components of the jitter of the deviation of the transition times in a signal on a signal line (44) from nominal bit times, a sampler (40) samples the signal at a rate...
5745533 Apparatus and method for adjusting the skew of a timing signal using propagation delay time of signals generated by a ring oscillator forming a digital circuit  
When a selector selects a first input terminal, a first loop circuit is formed including first and second input buffer circuits and an output buffer circuit. When the selector selects a second...
5727021 Apparatus and method for providing a programmable delay with low fixed delay  
A printed circuit board tester that compensates for the different propagation length of each channel including a single-input delay cell, at least one multiple-input delay cell, and a multiplexor....
5717729 Low skew remote absolute delay regulator chip  
A remote delay regulator circuit measures the effects of intrinsic propagation delays experienced by a system clock signal propagating through an extended clock distribution path that encompasses a...
5712883 Clock signal distribution system  
A system for distributing synchronous clock signals includes a set of spatially distributed deskewing stages. Each stage includes matching adjustable first and second delay circuits and a phase...
5712855 Apparatus for testing and measuring electronic device and method of calibrating its timing and voltage level  
The present invention is intended to provide a testing and measuring apparatus for accurately and quickly calibrating the input and output timing of a plurality of test signal patterns and voltage...
5712882 Signal distribution system  
A clock signal distribution system provides a set of synchronized, spatially distributed local clock signals. The system includes a source of periodic reference clock signal, a set of spatially...
5692009 Jitter measuring method and apparatus  
A jitter measuring method and apparatus is provided which is capable of measuring jitters in serial digital signals transmitted at a high bit rate. The method and apparatus detects from a serial...
5621774 Method and apparatus for synchronizing parallel data transfer  
A data transfer apparatus includes a transmitting apparatus having a pulse generation circuit for generating a plurality of data and a clock having a predetermined timing relation to the plurality...
5579352 Simplified window de-skewing in a serial data receiver  
A serial data receiver includes a clock recovery circuit, a data latch, and a selectable clock inversion mechanism coupled between the clock recovery circuit and the data latch. In one embodiment,...
5578938 Semiconductor integrated circuit having a clock skew test circuit  
A semiconductor integrated circuit has a test circuit capable of accurately measuring the clock skew of a clock signal in an LSI. The test circuit includes first and second flip flops driven by the...
5522088 Shared channel subsystem has a self timed interface using a received clock signal to individually phase align bits received from a parallel bus  
A shared channel subsystem has an input-output element for coupling each of a plurality of input-output controllers to each of a plurality of processor nodes by means of a self-timed interface...
5515403 Apparatus and method for clock alignment and switching  
In a telecommunication system having multiple timing subsystems receiving and distributing redundant timing signals, there is provided a circuitry for aligning first and second redundant timing...
5513377 Input-output element has self timed interface using a received clock signal to individually phase aligned bits received from a parallel bus  
An enhanced input-output element has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on...
5509038 Multi-path data synchronizer system and method  
A system and method for transferring data between clock domains operating at substantially the same frequency continuously compares the phase relationship of the clocks of the two domains and...
5498983 Device for checking the skew between two clock signals  
A device checks the skew between two clock signals among a plurality of clock signals having the same frequency. The two clock signals of each possible pair of clock signals respectively enable two...
5499190 System for measuring timing relationship between two signals  
A system for measuring timing relationship between two signals for accurately measuring a timing relationship between signals includes an electro-optic measuring unit and a waveform storage and...
5497462 Method and circuit for protecting circuit configurations having an electrically programmable non-volatile memory  
In a method and circuit for protecting circuit configurations having an electrically programmable non-volatile memory used as a non-volatile counter, an access check is provided in the circuit...
5491728 Cell resequencing system for a telecommunication network  
A cell resequencing system is provided for a resequencing section (RS) of a telecommunication network through which cells of communications are transmitted. The resequencing section includes cell...
5469477 Method and arrangement for minimizing skew  
A method and an arrangement minimizes skew in digital synchronous systems. The arrangement includes N number of driver circuits, each of which has a P number of buffer units, of which each has an...
5455831 Frame group transmission and reception for parallel/serial buses  
A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data...
5455830 Error detection and recovery in parallel/serial buses  
A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data...
5438259 Digital circuitry apparatus  
In a digital circuitry apparatus in which clock distribution can be performed with high accuracy even in the case where variations in delay time are caused by variations in the apparatus operating...
5436908 Common edge output skew detection circuit  
An output skew detection circuit detects and measures output skew tOSLH, tOSHL between multiple in phase common edge output signals propagated through a multiple signal driver circuit having n...
5434996 Synchronous/asynchronous clock net with autosense  
A circuit within a bus bridge operating in a first clock domain and a second clock domain, wherein the circuit allows data, address or any other information to be reliably transferred between the...
5428764 System for radial clock distribution and skew regulation for synchronous clocking of components of a computing system  
A radial clock distribution system that converts a standard bus clock signal into two pairs of inverted and non-inverted clocking signals. The two pairs of clocking signals have a lower frequency,...
5418538 Rapid satellite signal acquisition in a satellite positioning system  
A method for fast acquisition of Satellite Positioning System (SATPS) signals from a satellite-based positioning system, such as GPS or GLONASS, that does not require permanent storage of satellite...
5418360 Serial optical signal distribution system and method, and optical/electrical converter for implementation thereof  
A serial optical signal distribution system and method uses first and second coextending optical waveguides. First and second trains of light pulses are propagated through the first and second...
5408507 Extended range enhanced skew controller  
An apparatus and method for extending the range of a digital data network by enhancing skew control. The apparatus is a circuit for use in a network interface unit. The apparatus measures the...
5406590 Method of and apparatus for correcting edge placement errors in multiplying phase locked loop circuits  
A method of starting up a system clock that has been generated by a phase-locked loop and correcting edge placement errors during coasting periods of the phase locked loop, and circuitry for...
5392318 Method and apparatus for deskewing/resynchronizing data slices with variable skews  
Each data sending high speed circuit generating and sending a stream of data slices and a stream of clock pulses is provided with a sync pulse generation circuit for synchronously generating and...
5386420 Coding method for correction and detection of skewed transitions in parallel asynchronous communication systems  
A method and apparatus for encoding and decoding a (t 1 ,t 2 )-skew-tolerant (ST) (t 1 +s 1 ,t 2 +s 2 )-skew-detecting (SD) code, and for correcting and detecting skewed transitions in a parallel...
5384781 Automatic skew calibration for multi-channel signal sources  
An automatic skew calibration technique for a multi-channel signal source uses a cross-coupled flip-flop calibration circuit and a microprocessor to align the timing of a pair of signals from the...
5381416 Detection of skew fault in a multiple clock system  
A skew fault detection system for detecting clock skew between two clock phases utilizes a plurality of skew fault detection circuits each of which employs two D-type flip-flops. The clock...
5373535 Method and apparatus for digitally compensating digital clock skew for high speed digital circuits  
A digital clock reconstruction circuit comprising a first flip flop, a programmable delay chain, and a first assembly of gates is provided to digitally compensate an entering digital clock's skew...
5369640 Method and apparatus for clock skew reduction through remote delay regulation  
A remote delay regulator circuit measures the effects of intrinsic propagation delays experienced by a system clock signal propagating through an extended clock distribution path that encompasses a...
5341405 Data recovery apparatus and methods  
Data recovery apparatus for receiving two channels of data signal portions skewed in time and recovering from them two data signal portions synchronized with a con, non clock signal. The apparatus...
5313501 Method and apparatus for deskewing digital data  
In a computer system, parallel streams of digital data are transmitted from a source to a destination in bursts or packets. At the beginning of each burst all the parallel data signals contain a...
5293626 Clock distribution apparatus and processes particularly useful in multiprocessor systems  
Clock pulses from a master oscillator are distributed in a multiprocessor computer system so that they arrive at a large number of utilization points located in operating clusters of modules within...
5280533 Coding method for skewed transition correction in parallel asynchronous communication systems  
An algorithm for a (t 1 , t 2 )-tolerant code, and a method and apparatus for decoding same, for tolerating and detecting skewed transitions in a parallel asynchronous communication system without...
5280485 Coding method for skewed transition detection in parallel asynchronous communication system  
An algorithm for a (t 1 ,t 2 )-detecting code, and a method and apparatus for decoding same, for detecting skewed transitions in a parallel asynchronous communication system without...
5278902 Method and apparatus for transition direction coding  
The present invention provides a method and apparatus for encoding data in the context of a digital system for communicating binary information, including code words, over a communications channel....
5272729 Clock signal latency elimination network  
A process independent digital clock signal timing network is described for generating a chip clock substantially in phase with and offset by one cycle from an input clock signal. The timing network...
5264746 Logic circuit board with a clock observation circuit  
This logic circuit board with a clock observation circuit comprises a plurality of logic circuit IC chips and a clock supply IC chip to supply clock signal to such logic circuit IC chips mounted on...
5259006 Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like  
A method is provided for eliminating hold time violations in implementing high-speed logic circuits specified in circuit configuration data includes the steps of providing a synchronizer flip-flop...
5257144 Synchronization and automatic resynchronization of multiple incremental recorders  
A system capable of synchronizing and automatically resynchronizing multiple DCRSi units includes a monitor for monitoring respective channels output by each unit for frame sync words which have...
5231598 Direct digital synthesis measurement signal skew tester  
A skew tester (60) measures output timing skew parameters OSHL and OSLH between multiple output signals of an integrated circuit (IC) device under test (DUT) having an input and multiple outputs. A...
5163162 System and method for data recovery in multiple head assembly storage devices  
A systematic method for detecting which head in a multiple head storage device contains errors and may be misaligned, and correcting for misalignment so that the data can be recovered. The...
5157696 Digital signal time difference correcting circuit  
A digital signal time difference correcting circuit used in digital interface circuits for transmitting and receiving a plurality of digital signals. Prior art digital interface circuits in typical...
Matches 251 - 300 out of 390 < 1 2 3 4 5 6 7 8 >