Matches 151 - 200 out of 345 < 1 2 3 4 5 6 7 >
Match Document Document Title
6574699 Fast track reassign in a rotating storage media  
A reassign process is provided in a disk drive system including a plurality of tracks for storing data, each of the tracks being divided into a plurality of sectors, each sector having a...
6557117 Built-in self test for PLL module with on-chip loop filter  
An on-chip built-in self test apparatus for a phase locked loop module that resides on an integrated circuit, receives a reference clock signal and provides an output clock signal. The apparatus...
6557110 Channel-to-channel skew compensation apparatus  
A channel-to-channel skew compensation apparatus is provided with N number of frame synchronization circuits 11 for generating frame signals to indicate data position of parallel data on a common...
6549000 Semiconductor device testing apparatus having timing hold function  
There is provided a semiconductor device testing apparatus capable of greatly decreasing an interrupted time of a testing even if a board on which a test pattern supply path and/or a strobe pulse...
6505312 Integrated circuit tester  
Pins of an integrated circuit are provided with timing axis signals for testing in the time axis without discrepancies. An electro-optic probe in proximity to a plurality of contact points of a...
6486693 Method and apparatus for testing integrated circuit chips that output clocks for timing  
An automatic test system useful for testing source synchronous devices at high speed. The data outputs of the device under test are routed to channel circuitry within the test system through...
6479983 Semiconductor device testing apparatus having timing hold function  
There is provided a semiconductor device testing apparatus capable of greatly decreasing an interrupted time of a testing even if a board on which a test pattern supply path and/or a strobe pulse...
6477668 Signal generation circuit of semiconductor testing apparatus  
A signal is generated according to the waveform information designated by a program and outputted by the format channels 1 and 2 . Skew correction circuits 51 to 54 are provided...
6453431 System technique for detecting soft errors in statically coupled CMOS logic  
Circuit for detecting error transients in logic circuits due to atomic events or other non-recurring noise sources includes a first circuit coupled to a data line for sensing a first signal on the...
6430725 System and method for aligning output signals in massively parallel testers and other electronic devices  
Signal alignment circuitry aligns (i e., deskews) test signals from a massively parallel tester. A timing portion of each signal is received by a rising edge delay element, a falling edge delay...
6430720 Functional testing method and circuit including means for implementing said method  
The present invention relates to a method of functional testing of a logic circuit and to an integrated circuit for implementing the method. The method includes providing at least one test pattern...
6392404 Triggered integrated circuit tester  
A triggered integrated circuit (IC) tester in accordance with the invention organizes a test of an IC into a succession of test cycles. A vector generated prior to the start of each test cycle...
6370200 Delay adjusting device and method for plural transmission lines  
In simultaneous transmission of a signal using plural transmission lines, a synchronous cycle is set, plural signals A, B, C and D are simultaneously transmitted to the plural transmission lines,...
6331800 Post-silicon methods for adjusting the rise/fall times of clock edges  
A method for eliminating races commences with the testing of an integrated circuit for races. If a clock signal which is produced by the integrated circuit is deemed to be a cause of races, at...
6327678 Skew adjusting method in IC testing apparatus and pseudo device for use in the method  
There are provided a skew adjusting method capable of accurately conducting a skew adjustment in an IC testing apparatus comprising a plurality of pin cards and an IC socket, and a pseudo device...
6282676 Method and apparatus for testing and debugging integrated circuit devices  
A method for testing and debugging a first IC (integrated circuit) device by use of an error-free second IC device is provided in the invention. The second IC device is identical to the first IC...
6249887 Apparatus and method for predicting failure of a disk drive  
A system for predicting failure of a disk is provided. A test string of performance sensitive reads is built and calibrated. That is, the positioning time and spindle speed for each performance...
6219384 Circuit for determining clock propagation delay in a transmission line  
A clock distribution apparatus with active phase alignment which makes the incidence of a timing event occur essentially simultaneously at multiple physically remote destinations. The circuit uses...
6209072 Source synchronous interface between master and slave using a deskew latch  
A source synchronous interface between a master device and slave device is described. A master device having a plurality of deskew latches is coupled to a slave device via a bus. The master device...
6201746 Test method for high speed memory devices in which limit conditions for the clock are defined  
When high speed memory devices are tested using a tester having a lower operating frequency than the operational speed of the memory device, limit conditions for the tester signals are required to...
6192092 Method and apparatus for clock skew compensation  
A method and apparatus to compensate for skew in a processor clock signal. A first clock signal at a first location in the processor is compared with a reference clock signal. The first clock...
6182236 Circuit and method employing feedback for driving a clocking signal to compensate for load-induced skew  
A clock generation circuit is provided within an electronic computer system to adjust the phase of a clocking signal provided to various subsystems of the electronic system. A first phase-locked...
6173351 Multi-processor system bridge  
A bridge for a multi-processor system provides interfaces to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism arbitrates...
6158030 System and method for aligning output signals in massively parallel testers and other electronic devices  
Signal alignment circuitry aligns (i.e., deskews) test signals from a massively parallel tester. A timing portion of each signal is received by a rising edge delay element, a falling edge delay...
6151682 Digital signal processing circuitry having integrated timing information  
Digital signal processing circuitry implemented in ASICs or FPGAs is built by combining multi-component constructs (e.g. macrocells). These circuits may be modified to include a timing channel by...
6134284 Circuit and method for receiving system clock signals  
A clock receiver system (10) includes a clock receiver circuit (14), a phase-lock loop circuit (15), and a clock receiver mirror circuit (16). The clock receiver circuit (14) comprises a...
6105157 Salphasic timing calibration system for an integrated circuit tester  
An integrated circuit tester produces an output TEST signal following a pulse of a reference CLOCK signal with a delay that is a sum of an inherent drive delay and an adjustable drive delay. The...
6092030 Timing delay generator and method including compensation for environmental variation  
Apparatus for supplying a signal after a predetermined time delay comprises circuitry for generating a base delay signal that is synchronized to a stable master oscillator insensitive to changes in...
6079035 Parallel data skew detecting circuit  
A sample signal is sequentially transported through a plurality of serial shift registers in respective data channels. The sample signal varies between a pair of levels, namely a first level and a...
6067653 Data decorder and data decoding method  
Bit stream data that contains a digital video signal and character data is input to a decoding apparatus. Bit map character data is extracted by a demultiplexer 1 and supplied to a data decoder 7....
6038266 Mixed mode adaptive analog receive architecture for data communications  
The invention is a receiver front end for a data communications system having adaptive correction for intersymbol interference, DC offset, baseline wander, and flat loss and related method. Each of...
6008455 Method and arrangement for minimizing skew  
At a signal transmission rate of 1 Gb/s, the "bit time" is 1 ns. This corresponds to a bit length in an optical fibre of 0.2 m. In view of the fact that skew shall not exceed one-tenth of a bit...
5974575 Simulation device and method  
The simulation device and method exhaustively checks for the influence of skew in external input signals caused by numerous instances of unspecified tester skew to prevent testing problems when...
5966417 Cycle alignment circuit for multicycle time systems  
A chip-to-chip Cycle Alignment Circuit is implemented on the CP chip with a phased lock loop so that a chip knows what is the cycle of a connected chip. Once the PLL is locked, the timing...
5914963 Clock skew reduction  
A computer system has a skew compensation circuit for synchronizing the phase of a first periodic signal in one device with a second periodic signal in a second device connected to the first device...
5898742 Optimal design method and apparatus for synchronous digital circuits by retiming through selective flipflop positioning and electronic circuit configuration produced by executing the method  
Optimal design method and apparatus for synchronous digital circuits by retiming through selective flipflop positioning and electronic circuit configuration produced by executing the method. The...
5894226 IC testing apparatus  
An IC testing apparatus performs testing on a test device such as an IC using test signals each consisting of test pulses. The apparatus contains skew adjusting circuits, drivers and comparators....
5884236 Calibration method of IC tester  
A calibration method is provided for an IC tester which performs testing of ICs in association with a computer having a storage. A calibration file corresponding to results of calibration is stored...
5870404 Self-timed circuit having critical path timing detection  
A self-timed circuit for use a clocked logic system is disclosed that comprises a timing detection device for detecting a timing margin of a critical path, the critical path being a path that...
5854797 Tester with fast refire recovery time  
Automatic test equipment for semiconductor devices. The automatic test equipment contains numerous channels of electronic circuitry in which precisely timed test signal are generated. Significant...
5852640 Clock distribution apparatus with current sensed skew cancelling  
A clock distribution apparatus with active phase alignment which makes the incidence of a timing event occur essentially simultaneously at multiple physically remote destinations. The circuit uses...
5835501 Built-in test scheme for a jitter tolerance test of a clock and data recovery unit  
A jitter test system for a clock and data recovery unit (CRU) is comprised of a data generating apparatus, apparatus for clocking the data generating apparatus with a jittered clock, apparatus for...
5832047 Self timed interface  
A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The...
5822330 Method and system for dynamically adjusting signal skewing  
As SCSI systems increase in size, especially where there are a plurality of physically separate components, cables are often used to connect various components of the system, such as drives, to one...
5822329 Data-transmitter-receiver  
In transmitting and receiving signals between a plurality of units in a information processing system, signals can be transmitted and received between circuits operated by asynchronous clocks which...
5809034 Apparatus and method for operating electronic device testing equipment in accordance with a known overall timing accuracy parameter  
A method of operating electronic device test equipment in accordance with a known overall timing parameter includes the step of identifying a first set of time delays between a first set of...
5805603 Synchronous semiconductor memory device realizing high speed and accurate operation  
A synchronous semiconductor memory device is provided with a delay circuit between an input latch circuit and a pad. The synchronous semiconductor memory device can operate at a higher speed since...
5798935 Method and apparatus for sizing buffers to provide minimal skew  
Disclosed is a system for automatically generating tables of buffer data which can be used during integrated circuit design to select appropriate buffers for signal distribution networks. The...
5768283 Digital phase adjustment circuit for asynchronous transfer mode and like data formats  
A digital phase adjustment circuit adjusts the phase between cell signals and a start-of-cell marker. The circuit relies on a known data pattern in unassigned cell signals in order to determine the...
5748672 System for measuring jitter in a non-binary digital signal  
To measure various frequency components of the jitter of the deviation of the transition times in a signal on a signal line (44) from nominal bit times, a sampler (40) samples the signal at a rate...
Matches 151 - 200 out of 345 < 1 2 3 4 5 6 7 >