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7617331 |
System and method of double address detection
A plurality of detectors can be evaluated to determine if more than one has been assigned the same address. Responsive thereto, such detectors could be identified for follow-up maintenance, or...
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7558990 |
Semiconductor circuit device and method of detecting runaway
In an embodiment of the invention, if a microprocessor detects runaway of a CPU executing a program, it starts a recovery program. The runaway in the program execution is detected by monitoring...
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7555569 |
Quick configuration status
Described are techniques for obtaining configuration information and conditionally executing a system call in accordance with a specified configuration state. A host issues a request for...
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7539788 |
Data processing system for keeping isolation between logical partitions
When a subject of access of a transaction from an IO device is not any resource allocated to a logical partition to which the device having issued the transaction belongs, a report as an error is...
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7532526 |
Method and system for testing address lines
Method and systems are described for testing an address line inter-coupling a processor and a memory. The contents of a first address in the memory are initially compared with the contents of a...
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7526671 |
Network communication system
The network communication system is capable of communicating with many internal units at high speed, improving reliability of the system and decreasing a production cost and a development cost. The...
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7526526 |
System and method for transferring data
Methods for synchronously transmitting control data from a first device to a second device in a streaming data network and for transferring non-addressed data through a streaming data network are...
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7475166 |
Method and system for fully trusted adapter validation of addresses referenced in a virtual host transfer request
A method, computer program product, and distributed data processing system that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to validate that a direct memory access...
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7441149 |
Method and apparatus of recording data in the optical recording medium
The present invention relates to a recording medium and apparatus and method for managing a defective area of the recording medium. According to an embodiment, the method includes (a) determining...
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7421624 |
Data recovery apparatus and method used for flash memory
A data recovery apparatus and method used for a flash memory, which can recover data damaged or lost when power supplied to the flash memory is cut off while data operations are being consecutively...
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7418636 |
Addressing error and address detection systems and methods
Addressing error detection systems and methods are disclosed. A target address is written to a memory in an electronic system and subsequently output on an address path through which the memory is...
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7366873 |
Indirectly addressed vector load-operate-store method and apparatus
A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented,...
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7340588 |
Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code
This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code...
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7246272 |
Duplicate network address detection
A plurality of data packets encoded according to a first protocol are received which encapsulate data encoded according to a second protocol. A first source address is extracted from the packets...
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7200781 |
Detecting and diagnosing a malfunctioning host coupled to a communications bus
Techniques and apparatus are disclosed for detecting and responding to the malfunction of a host coupled to a communications bus through a bus transceiver.
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7181655 |
Method and circuit arrangement for memory error processing
The present invention relates to a method and circuit arrangement for performing an error correction in a memory arrangement in which a redundancy system is used. The addresses of faulty cells are...
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7120836 |
System and method for increasing cache hit detection performance
A system and method for increasing computing throughput through execution of parallel data error detection/correction and cache hit detection operations. In one path, hit detection occurs...
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7117398 |
Program counter range comparator with equality, greater than, less than and non-equal detection modes
An program counter address comparator includes two comparators comparing an input program counter address with respective reference addresses. The comparators produce a match indication on...
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7065680 |
Method and a system for evaluating the reliability of a program in an electronic device, and an electronic device
A method and associated system and electronic device for evaluating the reliability of a program ( 401 ) stored in a storage memory of an electronic device ( 1 ) having a processing memory ( 3 b )...
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7043502 |
Methodology for JEDEC file repair through compression field techniques
A method of generating a file suitable for programming a programmable logic device. The method generally comprises the steps of (A) generating a programming item from a plurality of parameters that...
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7043495 |
Techniques for JEDEC file information integrity and preservation of device programming specifications
A method of generating a file suitable for programming a programmable logic device. The method generally comprises the steps of (A) generating a programming item from a plurality of parameters that...
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6999386 |
Drive, method for reading data, information recording medium reproduction apparatus, and method for reproducing data having reading errors
A method for reading data from an information recording medium having a plurality of address regions, includes the steps of: performing a reading operation for all of designated address regions...
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6968479 |
Verifying data in a data storage device
The present invention relates to a storage device controller for controlling the operations of the data storage system. The controller includes error-correcting code (ECC) coding and decoding of...
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6944792 |
Method for verifying user memory validity in operating system
A method for verifying user memory validity which copes with faults generated in the Kernel area by returning an error value, even if the fault is generated by a user buffer address checking...
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6941493 |
Memory subsystem including an error detection mechanism for address and control signals
A memory subsystem includes a memory controller coupled to a memory module including a plurality of memory chips via a memory bus. The memory controller may generate a plurality of memory requests...
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6931571 |
Method and apparatus for handling transient memory errors
Method and apparatus for managing memory of a data processing system. In one embodiment, memory objects are allocated in response to memory allocation requests. Each object has an associated...
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6931476 |
Electronic apparatus with ROM data correction function
An electronic apparatus has in a CPU core an instruction correcting circuit that includes memory cells, a comparator and a selector. The memory cells store, when initializing the electronic...
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6901540 |
TLB parity error recovery
A microprocessor, data processing system, and method are disclosed for handling parity errors in an address translation facility such as a TLB. The microprocessor includes a load/store unit...
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6859897 |
Range based detection of memory access
Memory accesses in a data processing device ( 14 ) can be monitored by selecting, from among a plurality of available memory relationships ( 37, 82 ), a memory relationship relative to an address...
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6854075 |
Simultaneous and redundantly threaded processor store instruction comparator
A simultaneous and redundantly threaded, pipelined processor executes the same set of instructions simultaneously as two separate threads to provide fault tolerance. One thread is processed ahead...
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6845475 |
Method and apparatus for error detection
Automatic detection or correction of addresses, such as Uniform Resource Locators, that are user-entered may be provided. A code that is associated with an address may be entered when an address is...
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6845353 |
Interpage prologue to protect virtual address mappings
In a computer which translates instructions from a target instruction set to a host instruction set, a method for determining validity of a translation of a target instruction linked to an earlier...
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6829735 |
Computer system having a ROM correction unit
Each of a plurality of ROM correction units in a computer system includes a register for storing a subject address of an original instruction group having a bug, a comparator for comparing a...
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6823473 |
Simultaneous and redundantly threaded processor uncached load address comparator and data value replication circuit
A simultaneous and redundantly threaded, pipelined processor executes the same set of instructions simultaneously as two separate threads to provide fault tolerance. One thread is processed ahead...
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6763517 |
Automated analysis of kernel and user core files including searching, ranking, and recommending patch files
A computerized method for automatically analyzing a core file created by a computer system after an unexpected interrupt. The packages installed on the computer system are determined and patch...
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6754856 |
Memory access debug facility
A computer system includes instruction fetch circuitry for dispatching fetched instructions to a pipelined execution unit, data memory access circuitry and emulator circuitry for use in debug...
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6751757 |
Disk drive data protection using clusters containing error detection sectors
The present invention is related to methods and apparatus that can enhance the reliability of a hard drive by providing a built-in error check in the drive. Conventional hard drives can erroneously...
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6745346 |
Method for efficiently identifying errant processes in a computer system by the operating system (OS) for error containment and error recovery
The present invention relates to a method and system for efficiently identifying errant processes in a computer system using an operating system (OS) error recovery method that identifies if the...
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6738882 |
Concurrent multi-processor memory testing beyond 32-bit addresses
Memory about 4 Gbytes is tested using a DOS diagnostics program that remaps memory to a 32-bit addresses. In some embodiments, memory above 3 Gbytes is tested in 1 Gbyte blocks until the end of...
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6725189 |
Adapter for coupling a legacy operating system to a driver of an I/O channel which has an incompatible native operating system interface
An adapter program couples a legacy operating system to a driver program of an I/O channel which has an incompatible interface to a native operating system. The adapter program includes a...
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6715036 |
Method, system, and data structures for transferring blocks of data from a storage device to a requesting application
Disclosed is a method, system, program, and data structures for transferring data to a requesting application. A request is received for one or more blocks of data at contiguous addresses in a...
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6587973 |
Method and apparatus for implementing fault tolerant logic in a storage system
A mechanism for implementing fault tolerant logic in an information storage system is disclosed. The mechanism comprises an inhibit logic which is invoked when the first RUNOUT block of a link...
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6457067 |
System and method for detecting faults in storage device addressing logic
An improved fault detection system and method for detecting the occurrence of faults within the addressing logic of a storage device is provided. Data stored to a selected address within a storage...
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6347383 |
Method and system for address trace compression through loop detection and reduction
A method and system for compressing memory address traces based on detecting and reducing the loops that exist in a trace is disclosed. The method and system consists of two steps. In the first...
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6311298 |
Mechanism to simplify built-in self test of a control store unit
A control store unit having a control store address generator able to provide both the normal control store address generation functions, and the BIST/logout address generation functions. In...
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6275938 |
Security enhancement for untrusted executable code
Untrusted executable code programs (applets or controls) are written in native, directly executable code. The executable code is loaded into a pre-allocated memory range (sandbox) from which...
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6269458 |
Computer system and method for diagnosing and isolating faults
A computer system for diagnosing and isolating faults in the computer system. A first value is written from the processor using the bus a first address within the address space of a diagnostic...
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6226763 |
Method and apparatus for performing cache accesses
A method and apparatus for performing cache accesses. A comparator is coupled to a cache and a lookup parity bit line to perform error detection.
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6223299 |
Enhanced error handling for I/O load/store operations to a PCI device via bad parity or zero byte enables
Device selects lines from each I/O device are brought into a PCI host bridge individually so that the device number of a failing device may be logged in an error register when an error is seen on...
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6212648 |
Memory module having random access memories with defective addresses
The present invention provides a memory module having connective terminals and a plurality of random access memories connected through a first set of interconnections to the connective terminals....
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