|
Match
|
Document |
Document Title |
|
|
7603586 |
Intelligent stationary power equipment and diagnostics
Stationary power equipment including a sensing device configured to collect data associated with an operation of the equipment, and a data storage device configured for storing the collected data....
|
|
|
7596719 |
Microcontroller information extraction system and method
A system for debugging a device under test may include a processor register with a program count and a debug program register that receives the program count upon execution of an instruction by a...
|
|
|
7596420 |
Device manufacturing method and computer program product
A method is provided wherein a lithographic projection apparatus is used to print a series of test patterns on a test substrate to measure printed critical dimension as function of exposure dose...
|
|
|
7594140 |
Task based debugger (transaction-event-job-trigger)
The embodiments of the invention provide an apparatus, method, etc. for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises...
|
|
|
7590911 |
Apparatus and method for testing and debugging an integrated circuit
An integrated circuit includes a first deserializer that deserializes serial data containing at least one of test instructions and/or data in a first format. A monitor module communicates with the...
|
|
|
7590737 |
System and method for customized I/O fencing for preventing data corruption in computer system clusters
Systems, methods, apparatus and software can implement a flexible I/O fence mechanism framework allowing clustered computer systems to conveniently use one or more I/O fencing techniques. Various...
|
|
|
7577874 |
Interactive debug system for multiprocessor array
A debug network on a multiprocessor array includes communication channels, a master controller, and one or more individual debug units in communication with one or more of the processors. The...
|
|
|
7577755 |
Methods and apparatus for distributing system management signals
Methods and apparatus are provided for improving the distribution of system management signals within a computer system complex. Mechanisms are provided for transmission both within a box and...
|
|
|
7577560 |
Microcomputer logic development device
A microcomputer logic development device realizing high speed sampling RAM monitoring by connecting an existing RAM measurement device, provided with a first block providing functions corresponding...
|
|
|
7573862 |
System and method for optimizing network capacity in a cellular wireless network
A system and method is disclosed for increasing the efficiency of a cellular communication network, reduce ongoing operating costs and increase revenue. According to one aspect, a method is...
|
|
|
7562274 |
User data driven test control software application the requires no software maintenance
Methods and apparatus for performing a data driven test on a circuit including at least one built-in-self-test compatible device. In one embodiment, the method includes describing the device using...
|
|
|
7558984 |
Apparatus and method for test and debug of a processor/core having advanced power management
An interface unit is provided in a JTAG test and debug procedure involving a plurality of processor cores. The interface unit includes a TAP unit. A switch unit is coupled to the interface unit and...
|
|
|
7555683 |
Inventory determination for facilitating commercial transactions during diagnostic tests
The invention provides for facilitating e-commerce transactions between a client and a server over a network. In particular, a client, such as a client computing device, can perform a diagnostic...
|
|
|
7543198 |
Test data reporting and analyzing using data array and related data analysis
Reporting and/or analyzing test data from a plurality of tests of an array structure using a data array. One method includes obtaining the test data, and reporting the test data in a data array,...
|
|
|
7536597 |
Apparatus and method for controlling power, clock, and reset during test and debug procedures for a plurality of processor/cores
An interface unit is provided for use with a JTAG test and debug procedure involving a plurality of processor cores. The interface unit is provided with a logic unit that can translate test and...
|
|
|
7533302 |
Trace and debug method and system for a processor
A trace and debug method and system for a processor. The method includes the steps: (A) monitoring a program counter (PC); (B) determining if a processor core executes non-successive instruction in...
|
|
|
7529976 |
Multiple subsystem error reporting
To log errors of a plurality of subsystems, a master reporting tool provides a table identifying the subsystems and their interface protocol addresses with respect to a network. A subsystem reports...
|
|
|
7526679 |
Apparatus for developing and verifying system-on-chip for internet phone
Provided is an apparatus for developing and verifying a system-on-chip for an Internet phone. The object of the present invention is to provide the system-on-chip developing and verifying apparatus...
|
|
|
7519864 |
Automation test systems
An automated testing system is provided that includes a computer system, a handset, script and scripting interface, a test module, and a data comparison component. The handset has at least one...
|
|
|
7516363 |
System and method for on-board diagnostics of memory modules
A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving...
|
|
|
7516362 |
Method and apparatus for automating the root cause analysis of system failures
A method for analyzing the root cause of system failures on one or more computers. An event is generated when a computer system detects a system failure. The cause of the failure is determined. The...
|
|
|
7512778 |
Method for sharing host processor for non-operating system uses by generating a false remove signal
A method for using an operating system device for non-operating system uses. A false event signal is generated to indicate that a device should be shut down. After this is accomplished, the device...
|
|
|
7502447 |
Call failure recording
A method and device for recording call failure information in a data transmission system is provided. The failure logs generated in response to a failure event include a failure type and a first...
|
|
|
7487400 |
Method for data protection in disk array systems
A method and a system for implementing the method are disclosed relating to archival storage of information in large numbers of disk units. The reliability of the stored information is checked...
|
|
|
7484123 |
Micro telecommunications computing architecture, MicroTCA, test system and method
A Micro Telecommunications Computing Architecture, MicroTCA, test system comprises an interconnect for communication between modules of the MicroTCA test system. A test controller module, such as a...
|
|
|
7484122 |
Controlling timing of execution of test instruction by target computing device
Controlling the timing of execution of test instructions by a target computing device is disclosed. A method initiates a test process at each target computing device. The method receives a process...
|
|
|
7480602 |
System verification test using a behavior model
The present invention provides a system verification system that automatically generates a behavior model modeling the system under test in terms of actions of a test case and a range of expected...
|
|
|
7478281 |
System and methods for functional testing of embedded processor-based systems
Functional testing of an embedded system is performed by a test control system that implements a peripheral emulation module to interface with an externally accessible port of the embedded system....
|
|
|
7475313 |
Unique pBIST features for advanced memory testing
This invention is new built-in self test instructions. A pointer register stores data identifying one bit of a data register. That bit determines whether the data of another data register is used...
|
|
|
7464295 |
Software programmable verification tool having multiple built-in self-test (BIST) modules for testing and debugging multiple devices under test (DUT)
Aspects of the invention may include testing and debugging an embedded device under test. Testing and debugging and embedded device under test may include the step of loading an instruction into a...
|
|
|
7444574 |
Stimulus extraction and sequence generation for an electric device under test
A method and system that utilizes a graphical interface that enables a user to select and capture building blocks of a Device Under Test (DUT) test scenario from a previously run test case or from...
|
|
|
7444573 |
VLCT programmation/read protocol
An integrated circuit with built-in self test enables internal data registers to be written to or read from via an external tester. In a command phase the programmable built-in self test unit...
|
|
|
7444546 |
On-board diagnostic circuit for an integrated circuit
An integrated circuit having a plurality of functional circuits interconnected via a functional bus is provided with a diagnostic bus-master circuit which uses bus transactions on the functional...
|
|
|
7437618 |
Method in a processor for dynamically during runtime allocating memory for in-memory hardware tracing
A method, apparatus, and computer program product are disclosed in a processor for dynamically, during runtime, allocating memory for in-memory hardware tracing. The processor is included within a...
|
|
|
7430688 |
Network monitoring method and apparatus
A network monitoring method and system reduces a load to a monitoring network without deteriorating accuracy of detecting a malfunction. A plurality of network constituent elements that constitute...
|
|
|
7424642 |
Method for synchronization of a controller
A system and method for reintegration of a redundant controller after occurrence of a fault is provided, comprising synchronizing outputs of a primary controller with outputs of secondary...
|
|
|
7421384 |
Semiconductor integrated circuit device and microcomputer development supporting device
During software development, a multichip module is used which encloses a target chip and a development chip in one package. A CPU of the development chip fetches instructions from a flash memory in...
|
|
|
7418631 |
Program-controlled unit
A program-controlled unit has debug resources for monitoring the operations proceeding within the program-controlled unit. The program-controlled unit described is distinguished by the fact that...
|
|
|
7415700 |
Runtime quality verification of execution units
One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor with multiple execution units of a same type. The method includes selecting one of the...
|
|
|
7401260 |
Apparatus, system, and method for performing storage device maintenance
An apparatus, system, and method are disclosed for performing a storage device maintenance operation. A management module receives a command through an interconnection module configured as a...
|
|
|
7401259 |
System and method for scenario generation in a distributed system
A system and method may emulate scenarios for testing a distributed system. The distributed system may include a plurality of nodes, each having one or more resources. The system may include a...
|
|
|
7395466 |
Method and apparatus to adjust voltage for storage location reliability
According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at...
|
|
|
7395462 |
Defect estimation apparatus and related method
A weighted defect estimating apparatus and a related method for determining a defect estimation value are disclosed. The weighted defect detecting apparatus includes: a defect detecting unit for...
|
|
|
7392441 |
Method of performing operational validation with limited CPU use of a communications network
A system, apparatus, computer program product and method of performing operational validation on a system are provided. The system may include a CPU with a cache, a communications network, and a...
|
|
|
7389455 |
Register file initialization to prevent unknown outputs during test
A system and method for initializing a register file during a test period for an integrated circuit, wherein the register file has one or more input ports. A counter, when enabled, is initialized...
|
|
|
7386761 |
Diagnostic repair system and method for computing systems
A diagnostic system and method for repairing computing devices comprises a diagnostic application running on a same computing system having a failed operating system (O/S). The diagnostic...
|
|
|
7370101 |
Automated testing of cluster data services
Methods and apparatus, including computer program products, implementing and using techniques for testing a data service on a computing cluster having several computing nodes. A test package is...
|
|
|
7367016 |
Method and system for expressing the algorithms for the manipulation of hardware state using an abstract language
A method for expressing the algorithms for the manipulation of hardware includes providing program instructions that describe a sequence of one or more transactions for manipulating hardware...
|
|
|
7334160 |
Method and apparatus for managing a distributed x-ray system
A preferred embodiment of the present invention provides a method and system for managing a distributed medical diagnostic imaging system. The system includes a system manager for managing the...
|
|
|
7331043 |
Detecting and mitigating soft errors using duplicative instructions
Software techniques are employed to mitigate soft errors. In particular, a compiler (or other executable code generator) may emit otherwise duplicative instructions targeting otherwise duplicative...
|