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7558722 |
Debug method for mismatches occurring during the simulation of scan patterns
A method and system are disclosed for testing for double shift errors in at least one scan chain of flip-flops during a simulation of the design of a digital integrated circuit chip. At the start...
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7559053 |
Program and system performance data correlation
System performance data and program performance data may be collected, converted into the same format and correlated by time. A graph or other display of system performance data over a time period...
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7555686 |
Semiconductor device, test board for testing the same, and test system and method for testing the same
Provided are a semiconductor device, a test board, and a test system and method for testing a semiconductor device. The semiconductor device includes an input terminal to which test pattern data is...
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7552360 |
Debug and test system with format select register circuitry
A system and method for sharing a communications link between multiple protocols is described that comprises a system comprising a communications interface configured to exchange information with...
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7548842 |
Scalable system for simulation and emulation of electronic circuits using asymmetrical evaluation and canvassing instruction processors
A scalable system for verifying electronic circuit designs in anticipation of fabrication by compiling a hardware description to instructions for canvassing processors and instructions for circuit...
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7546491 |
Semiconductor memory device with standby current failure judging function and method for judging standby current failure
A semiconductor memory device which a pad for receiving a power voltage, a first power line connected to the pad, and a plurality of second power lines respectively connected to memory cells of a...
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7539913 |
Systems and methods for chip testing
Circuit and method for testing digital logic circuit modules of an integrated circuit chip. The circuit includes a storage device, a first multiplexing module and a selection device. The storage...
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7539900 |
Embedded microprocessor for integrated circuit testing and debugging
A technique for embedding a microprocessor into an integrated circuit allows on-chip testing and debugging. The microprocessor present on the chip tests and debugs the rest of the chip. Both...
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7536597 |
Apparatus and method for controlling power, clock, and reset during test and debug procedures for a plurality of processor/cores
An interface unit is provided for use with a JTAG test and debug procedure involving a plurality of processor cores. The interface unit is provided with a logic unit that can translate test and...
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7533315 |
Integrated circuit with scan-based debugging and debugging method thereof
An integrated circuit comprises a test interface, an embedded in-circuit emulator, a circuit-under-debugging, and a memory. The embedded in-circuit emulator is used for software debugging via the...
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7533312 |
System and method for testing of electronic circuits
The system and method of the present invention combine multiple tests ( 15 ) into a batch and submit the batch for processing to exercise electronic circuits, for example, a managed network ( 25 )...
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7533316 |
Method and apparatus for disabling and swapping cores in a multi-core microprocessor
In some embodiments, a method and apparatus for disabling and swapping cores in a multi-core microprocessor are presented. In this regard, a test agent is introduced to disable a core, to configure...
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7526679 |
Apparatus for developing and verifying system-on-chip for internet phone
Provided is an apparatus for developing and verifying a system-on-chip for an Internet phone. The object of the present invention is to provide the system-on-chip developing and verifying apparatus...
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7526422 |
System and a method for checking lock-step consistency between an in circuit emulation and a microcontroller
A system and a method for checking consistency of a lock-step process while debugging a microcontroller code. A host device copies a partially copies a production microcontroller in an ICE...
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7521950 |
Wafer level I/O test and repair enabled by I/O layer
A 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization...
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7523351 |
System and method for providing mutual breakpoint capabilities in computing device
A system having at least one breakpoint generating module and a core processor and method for providing mutual breakpoint capabilities to at least one breakpoint generating module and a core...
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7523368 |
Diagnostics unit using boundary scan techniques for vehicles
A test system including a diagnostics unit comprising a plurality of diagnostics-unit interfaces to communicatively couple the diagnostic unit to a plurality of units under test and a unit...
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7523010 |
Automated circuit board test actuator system
A method for automatically inserting connectors and coupling test probes to circuit boards, such as computer system boards and the like. The method is implemented via an apparatus that enables...
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7519862 |
Software programmable verification tool having a single built-in self-test (BIST) module for testing and debugging multiple memory modules in a device under test (DUT)
Aspects of the invention for testing and debugging an embedded device under test may include the step of loading an instruction into a parameterized shift register of a BIST module coupled to each...
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7519886 |
Apparatus and method for integrated functional built-in self test for an ASIC
We describe, in exemplary embodiments, an on-chip Functional Built-In Self Test (“FBIST”) mechanism for testing integrated circuits with internal memory state and complex transaction based...
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7519889 |
System and method to reduce LBIST manufacturing test time of integrated circuits
A method to reduce logic built in self test manufacturing test time of integrated circuits, comprising: loading a plurality of test seeds in bulk into a locally accessible on-chip memory array...
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7519863 |
Detection of a malfunction in a hardware module
A method of detecting a malfunction in a hardware module is shown. The hardware module comprises a functional hardware adapted to provide a defined function and a diagnosis component. The diagnosis...
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7519496 |
Electronic circuit comprising a secret sub-module
The invention relates to an electronic circuit including a sub-module assembly ( 2 ) connected to the rest of the circuit, the sub-module assembly including a secret sub-module ( 4 ) for performing...
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7516376 |
Test pattern generator, test circuit tester, test pattern generating method, test circuit testing method, and computer product
A test circuit tester includes a scan-chain input-output information generator that generates information for an input and an output of the scan chain that is scan-chain input-output information,...
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7512853 |
***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Semiconductor integrated circuit and method for testing the same
In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply...
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7512772 |
Soft error handling in microprocessors
A method for low cost handling of soft error in a microprocessor system is described, which includes detecting a soft error, indicating a register having soft error to an instruction unit, flushing...
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7512727 |
Redundant control system having a peripheral unit for an automation device
There is described a periphery unit for an automatic device, which can be actuated as an analog input and as an analog output. A number of connections which are to be used as inputs and the number...
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7509533 |
Methods and apparatus for testing functionality of processing devices by isolation and testing
A computerized device having a first processing device, a second processing device, and an interconnection mechanism allowing communication between the first and second processing devices, provides...
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7505872 |
Methods and apparatus for impact analysis and problem determination
A technique for determining an impact of a condition (e.g., service outage) of at least one subject component in a computing environment comprises the following steps/operations. First, one or more...
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7506234 |
Signature circuit, semiconductor device having the same and method of reading signature information
A signature circuit in a semiconductor chip includes a signature program circuit configured to be programmed with signature information and to output a signature signal in response to the signature...
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7506205 |
Debugging system and method for use with software breakpoint
Methods and systems are provided for debugging a program executing on a processor. In a first implementation, a processing system includes a processor configured for switching to a debug mode from...
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7502965 |
Computer chip set having on board wireless interfaces to support test operations
A method and apparatus are provided for an embedded wireless interface that is embedded in, for example, one of an input and output controller device for controlling input and output communications...
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7502963 |
Optimization by using output drivers for discrete input interface
The invention relates to design optimization of microprocessors using spare driver outputs for discrete input interfaces. An output driver or pre-FET driver is used to interface a discrete input...
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7500164 |
Method for testing an integrated circuit device having elements with asynchronous clocks or dissimilar design methodologies
A method for testing an integrated circuit device with asynchronous clocks or dissimilar design methodologies is provided. With the method, each clock domain has its own scan paths that do not...
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7500147 |
Test system and method
A test system includes a terminal host and a to-be-tested circuit board. The terminal host generates a trigger signal. The to-be-tested circuit board includes a system chip, a memory and a...
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7496792 |
Repeat digital message transmission between a microprocessor monitoring circuit and an analyzing tool
The invention concerns a method for transmitting digital messages through output terminals ( 22 ) of a monitoring circuit ( 18 ) incorporated in a microprocessor ( 12 ) during execution of a series...
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7496813 |
Communicating simultaneously a functional signal and a diagnostic signal for an integrated circuit using a shared pin
An integrated circuit 2 including functional circuits 4, 6 and a diagnostic circuit 10 passes a functional signal and a diagnostic signal to/from the integrated circuit using a shared...
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7493516 |
Hardware-error tolerant computing
Embodiments include a computing system, a device, and a method. A computing system includes a processor subsystem having an adjustable operating parameter. The computing system also includes an...
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7493542 |
Arrangement for testing integrated circuits
The invention relates to an arrangement for testing integrated circuits, to a test system ( 2 ), to a circuit ( 1 ) to be tested, and to a method of testing logic circuits, where the test system (...
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7492718 |
Serial protocol controller that supports subroutine calls
Described is a protocol controller that supports calls to a packet subroutine which includes a packet processing engine programmed to retrieve packets from a packet memory and to interpret the...
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7487414 |
Parallel bit test circuits for testing semiconductor memory devices and related methods
An integrated circuit device includes a test circuit and at least one flag generator circuit. The test circuit is configured to generate first and second sets of test results in parallel in...
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7487421 |
Emulation cache access for tag view reads
A built-in self test unit reads tag bits of a predetermined cache entry and outputs these tag bits via an external interface. The built-in self test unit enters an emulation mode upon receipt of an...
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7487419 |
Reduced-pin-count-testing architectures for applying test patterns
Methods, apparatus, and systems for testing integrated circuits using one or more boundary scan cells are disclosed. The methods, apparatus, and systems can be used, for example, to apply at-speed...
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7487398 |
Microprocessor design support for computer system and platform validation
Elements of a computer system are tested by generating harassing transactions on a bus. A first transaction is detected on the bus. The first transaction including a first data request to a first...
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7487397 |
Method for cache correction using functional tests translated to fuse repair
A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory,...
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7484150 |
Semiconductor integrated circuit design apparatus and semiconductor integrated circuit design method
A semiconductor integrated circuit design method is a method for designing a semiconductor integrated circuit having a main circuit as well as the spare cell including a scan flip-flop. In the...
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7484140 |
Memory having variable refresh control and method therefor
A memory ( 10 ) has a memory array ( 12 ), a charge pump ( 18 ), a voltage regulator ( 20 ), a refresh control circuit ( 16 ), and a refresh counter ( 22 ). The charge pump ( 18 ) provides a...
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7484135 |
Semiconductor device having a mode of functional test
A semiconductor device includes a circuit block; a first signal path for guiding a test signal to a signal input terminal of the circuit block; a second signal path for guiding a test clock to a...
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7480824 |
Method for controlling starting operation of unit and executing self-checking test
When a testing system is connected to a debug port of a tape drive unit or a SCSI bus, a self-checking test for a fabricating process is executed. When the testing system is not connected, the...
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7480882 |
Measuring and predicting VLSI chip reliability and failure
This embodiment replaces the use of LBIST to get a pass or no-pass result. A selective signature feature is used to collect the top failing paths, by shmooing the chip over a cycle time. These...
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