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7624362 |
Circuit analysis device using processor information
A circuit analysis device comprises a first storing unit operable to store an execution object which can operate on a real processor and includes information of a logical circuit, an analyzing unit...
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7620842 |
Method for highly available transaction recovery for transaction processing systems
A highly available transaction recovery service migration system in accordance with one embodiment of the present invention implements a server's Transaction Recovery Service (TRS) as a migratable...
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7620841 |
Re-utilizing partially failed resources as network resources
A method and apparatus for re-utilizing partially failed compute resources in a massively parallel super computer system. In the preferred embodiments the compute node comprises a number of clock...
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7613961 |
CPU register diagnostic testing
One embodiment disclosed relates to a method of compiling a program to be executed on a target central processing unit (CPU). The method includes opportunistically scheduling diagnostic testing of...
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7607040 |
Methods and systems for conducting processor health-checks
Systems and methods for conducting processor health-checks are provided. In one embodiment, a method for evaluating the status of a processor is provided. The method includes, for example,...
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7607038 |
Systems and methods for CPU repair
In one embodiment, a method for repairing a faulty cache element is provided. Once a monitored cache element is determined to be faulty, the system stores the repair information, and cache...
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7600152 |
Configuring cache memory from a storage controller
Disclosed are a storage controller, and a method of operating a storage controller, for interfacing between host systems and a storage devices system. The storage controller includes a first...
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7596790 |
Allocating computing resources in a distributed environment
In one embodiment of the present invention, a computing system includes a plurality of systems coupled in a distributed infrastructure, and a resource allocator to allocate activities of an...
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7590990 |
Computer system
A general-purpose OS (operating system) is used as a host OS and a real-time OS operating as one or more tasks on the host OS is used as a guest OS. An interrupt handler and a task on the host OS...
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7590719 |
System and a method for blocking off processors when communication paths between adapters and a cache memory are determined to be secure
The invention relates to exchanging micro programs in a storage device, automatically, without halting operation. In one embodiment, the path adapters of a host computer are connected to the...
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7587632 |
High availability, high performance software component architecture
A high availability, high performance software component architecture includes a primary configuration and at least one secondary configuration to take over from the primary configuration in the...
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7587523 |
Distributed systems for determining card status
The master/slave arbitration process includes a voting process that allows cards within the system to use voting to determine the health of each of the individual cards. The voting process thereby...
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7583774 |
Clock synchroniser
A clock synchronizer, for generating a local clock signal synchronized to a received clock signal, is described and claimed, along with a corresponding clock synchronization method. The clock...
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7571346 |
System and method for interoperability application driven error management and recovery among intermittently coupled interoperable electronic devices
System, device, method, and computer program and computer program products for providing communicating between devices having similar or dissimilar characteristics and facilitating seamless...
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7562265 |
Method, apparatus and program storage device for providing self-quiesced logic to handle an error recovery instruction
A method, apparatus and program storage device for providing self-quiesced logic for handling an error recovery instruction such as a reset or self-test instruction. For example, during a reset or...
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7562253 |
Segmented protection system and method
A segmented protection system and method. The invention comprises a plurality of Processing Modules arranged in series along a Protection Bus. A number of Protection Groups may be formed along the...
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7549081 |
Processor array
An array of processing elements can incorporate a degree of redundancy. Specifically, the array includes one or more spare, or redundant, rows of array elements, in addition to the number required...
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7549077 |
Automated self-forming, self-healing configuration permitting substitution of software agents to effect a live repair of a system implemented on hardware processors
A configuration for use with a processor that incorporates a suite of “flat” hardware architecture and superimposes thereon a self-forming, self-healing, hierarchical architecture implemented...
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7546487 |
OS and firmware coordinated error handling using transparent firmware intercept and firmware services
Methods and architectures for performing hardware error handling using coordinated operating system (OS) and firmware services. In one aspect, a firmware interface is provided to enable an OS to...
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7543095 |
Managing input/output interruptions in non-dedicated interruption hardware environments
Input/output interruptions are managed in computing environments that do not use dedicated per-guest interruption hardware to present interruptions. Dispatchable guest programs in the environment...
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7536687 |
System and method for automatic installation of embedded software packages
The system and method facilitates transition from one software packaging model to a new model. New software packages include a capability package and an enabler package. The capability package...
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7536589 |
Processing apparatus
A processing apparatus includes a plurality of operation units each of which performs a given operation for an input operand in accordance with an operating instruction and outputs an exception...
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7533294 |
Functional coverage driven test generation for validation of pipelined processors
A functional coverage based test generation technique for pipelined architectures is presented. A general graph-theoretic model is developed that can capture the structure and behavior...
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7529998 |
Runtime reconfiguration of reconfigurable circuits
A reconfigurable circuit having primary function blocks with runtime built-in self-test (BIST) circuitry, one or more redundant function blocks and runtime reconfiguration logic is described herein.
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7529972 |
Methods and apparatus for reconfiguring a storage system
One embodiment relates to a computer system comprising at least one host, at least one object addressable storage (OAS) system and at least one communication medium that couples the at least one...
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7526639 |
Method to enhance boot time using redundant service processors
A computer implemented method and system for enhancing boot time of a computer system. Initial program load firmware is initialized on a plurality of service processors. The plurality of service...
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7519975 |
Method and apparatus for exception handling in a multi-processing environment
A method and apparatus for exception handling in a multi-processor environment are described. In an embodiment, a method for handling a number of exceptions within a processor in a multi-processing...
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7519855 |
Method and system for distributing data processing units in a communication network
A method and system for distributing a plurality of data processing units ( 116, 118, 120, 122, 124, 126, 128, 130 and 132 ) in a communication network ( 100 ) is provided. The communication...
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7516358 |
Tuning core voltages of processors
A method, apparatus, and system are disclosed for tuning core voltages of processors. One embodiment is a method for software execution. The method includes varying core voltages of plural...
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7512837 |
System and method for the recovery of lost cache capacity due to defective cores in a multi-core chip
A method for recovering lost cache capacity in a multi core chip having at least one defective core including identifying the cores contained in the chip that are viable cores and identifying at...
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7512825 |
Responding to DC power degradation
Systems, methodologies, media, and other embodiments associated with detecting and responding to a degradation of a direct current provided to a frequency scalable processor are described. One...
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7509375 |
Management system for multimodule multiprocessor machines
The present invention relates to a global management system for a multimodule, multiprocessor machine (PK). The system is characterized in that it comprises an independent module (SM) dedicated to...
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7502963 |
Optimization by using output drivers for discrete input interface
The invention relates to design optimization of microprocessors using spare driver outputs for discrete input interfaces. An output driver or pre-FET driver is used to interface a discrete input...
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7502954 |
High availability data storage system
A data storage system includes a disk drive array including a plurality of disk drives; a first storage processor for controlling the operation of the data storage system; a second storage...
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7500139 |
Securing time for identifying cause of asynchronism in fault-tolerant computer
A fault-tolerant computer has a pair of duplex systems having respective CPU subsystems that are operable identically in lock-step synchronism. Each of the duplex systems has a CPU, a main storage...
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7500138 |
Simplified event selection for a performance monitor unit
A method and a processor for counting events in a performance monitor unit (PMU) of the processor includes using a mask bit and match bit comparison for event data to determine occurrence of events...
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7496788 |
Watchdog monitoring for unit status reporting
Systems and methods for monitoring the accuracy of unit status reporting within an application specific integrated circuit device may be used reduce power consumption. Accurate status reporting of...
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7496782 |
System and method for splitting a cluster for disaster recovery
The present invention provides a system and method for disaster recovery split of a node from a cluster to enable cluster management operations using quorum-based data replication services to...
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7493618 |
Fault tolerant mutual exclusion locks for shared memory systems
The present invention provides a method of implementing a fault-tolerant mutual exclusion lock. The present invention records in a lock structure the IDs of all processes whose failure can lead to...
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7493516 |
Hardware-error tolerant computing
Embodiments include a computing system, a device, and a method. A computing system includes a processor subsystem having an adjustable operating parameter. The computing system also includes an...
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7493515 |
Assigning a processor to a logical partition
Assigning a processor to a logical partition in a computer supporting multiple logical partitions that include assigning priorities to partitions, detecting a checkstop of a failing processor of a...
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7484125 |
Method and apparatus for providing updated processor polling information
Embodiments of the invention provide a method and an apparatus to collect and dynamically update processor polling information. In one method embodiment, the present invention collects processor...
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7480821 |
Method for encoding/decoding a binary signal state in a fault tolerant environment
A method for use in a fault tolerant environment for assuring that devices within the environment switch between primary and back-up systems in response to remotely generated control signals. In...
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7480816 |
Failure chain detection and recovery in a group of cooperating systems
A cluster or group of cooperating systems may implement failure chain detection and recovery. The group may include multiple nodes and each node may include a group management services (GMS) module...
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7478272 |
Replacing a failing physical processor
Replacing a failing physical processor in a computer supporting multiple logical partitions, where the logical partitions include dedicated partitions and shared processor partitions, the dedicated...
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7478263 |
System and method for establishing bi-directional failover in a two node cluster
A system and method for permitting bi-directional failover in two node clusters utilizing quorum-based data replication. In response to detecting an error in its partner the surviving node...
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7467325 |
Processor instruction retry recovery
Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or...
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7467322 |
Failover method in a cluster computer system
In a computer system having a cluster configuration, a reset command issued from each of computers to any of the other computers is transmitted to a reset control unit. A control module of the...
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7467179 |
Backplane architecture for a data server
A media server for use in networks where media are transmitted in packet form comprises at least one card shelf containing at least one bus controller card, at least one other card such as a media...
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7454654 |
Multiple parallel pipeline processor having self-repairing capability
A multiple parallel pipeline digital processing apparatus has the capability to substitute a second pipeline for a first in the event that a failure is detected in the first pipeline. Preferably, a...
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