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7620828 |
Dynamically changing PCI clocks
A method, apparatus and computer-usable medium are presented for dynamically selecting a clock signal used by a peripheral device that is coupled to a motherboard. When the motherboard is powered...
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7590880 |
Circuitry and method for detecting and protecting against over-clocking attacks
The present invention is directed to circuitry for detecting and protecting against over-clocking attacks on hardware modules. The circuitry preferably comprises a test signal, a delay path for...
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7581133 |
System and method of providing real time to devices within a server chassis
An information management system is disclosed and can include a server chassis having a chassis control panel. The chassis control panel can include a real time clock. Further, the system can...
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7574618 |
Interface circuit
Noise removal and detection are performed for a signal VBUS in a detection portion in accordance with a low-frequency clock signal CLK generated by a CR oscillation circuit, and a detection signal...
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7568118 |
Deterministic operation of an input/output interface
In one embodiment, the present invention includes a method for receiving data from a second device in a first device, forwarding the data from an input/output (I/O) clock domain to a system clock...
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7539885 |
Method and apparatus for adaptive CPU power management
A method and apparatus are disclosed for performing adaptive run-time power management in a system employing a CPU and an operating system. A CPU cycle tracker (CCT) module monitors critical CPU...
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7519849 |
Technique for providing service processor access to control and status registers of a module
A technique for providing service processor (SP) access to registers, e.g., control and status registers (CSRs), located within hardware modules of a computer system, ensures access to the CSRs...
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7519847 |
System and method for information handling system clock source insitu diagnostics
A clock diagnostics module, such as a state machine, integrated into an integrated clock controller monitors clock signals associated with the integrated clock controller and reports the status of...
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7478255 |
Clock distribution in multi-cell computing systems
Embodiments of the invention relate to distribution of clocks to CPUs in processing cells of a multi-cell system. In an embodiment, each cell includes an interface, referred to as an agent. A...
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7471333 |
Image sensing device interface unit
The image sensing device interface unit attached to an image sensing device has dedicated means to detect a complete missing line and to perform clock gating of circuits for power management...
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7469357 |
Method and apparatus for dynamic power management in an execution unit using pipeline wave flow control
Power is conserved by dynamically applying clocks to execution units in a pipeline of a microprocessor. A clock to an execution unit is applied only when an instruction to the execution unit is...
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7451338 |
Clock domain crossing
Provided are a method, system, and device to effectuate a transfer of data from one clock domain to another. In accordance with one aspect of the description provided herein, bits of data to be...
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7444533 |
Method and device for the sampling of digital data in synchronous transmission, with maintenance of binary integrity
The method is applicable to the reception of data in the case of a digital transmission in which the pieces of data are transmitted by a unit of equipment A to a unit of equipment B with an...
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7444529 |
Microcomputer having rewritable nonvolatile memory
A CPU, when shifting to a sleep mode, discontinues the oscillating operations of an oscillation circuit and of a frequency multiplier circuit through a low power consumption control circuit. A...
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7437584 |
Apparatus and method for reducing power consumption in electronic devices
An apparatus and method for reducing power consumption in a programmable logic device (PLOD) having multiple logic blocks and macrocells. Power consumption is reduced by detecting programmable...
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7421607 |
Method and apparatus for providing symmetrical output data for a double data rate DRAM
An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a...
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7421606 |
DLL phase detection using advanced phase equalization
A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is...
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7409568 |
Power supply voltage droop compensated clock modulation for microprocessors
A voltage source droop compensated clock modulation for microprocessors is described. Specifically, the circuit reduces the clock frequency if a voltage source droop is detected.
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7403122 |
RFID tag circuits operable at different speeds
Embodiments of RFID tag circuits and methods are described, which include a chip having a clock circuit operable to generate a clock signal having different frequencies, and one or more components...
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7395449 |
Method and apparatus for limiting processor clock frequency
A method and apparatus for limiting a processor clock frequency includes an overclocking prevention circuit. The overclocking prevention circuit includes a frequency limiting circuit having...
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7380152 |
Daisy chained multi-device system and operating method
A multi-device system having a daisy chain system bus structure and related method of operation are disclosed. A reference signal having a defined oscillation period is communicated around the...
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7376857 |
Method of timing calibration using slower data rate pattern
An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than...
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7376856 |
Circuit arrangement
An object of the present invention is to provide a circuit device in which the power consumption can be reduced without the dedicated signal. A circuit device ( 1 ) comprising a D flip-flop (F 0 )...
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7370191 |
Method and device for playing compressed multimedia files in semi-power on state of a computer
A method and device for playing compressed multimedia files in a semi-power on state of a computer is provided. A program is provided in the BIOS so that POST (Power On Self Test) is not performed...
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7366938 |
Reset in a system-on-chip circuit
An electronic device having first circuitry operating in a first clock environment and second circuitry operating in a second clock environment, the first circuitry being arranged to generate a...
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7366937 |
Fast synchronization of a number of digital clocks
The present invention relates to a method for synchronizing a number of digital clocks to a synchronizing signal, said method comprising generating centrally a reference clock, synthesizing said...
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7350096 |
Circuit to reduce power supply fluctuations in high frequency/ high power circuits
The present invention provides for a circuit for transitioning clocking speeds. A counter is coupled to the clocking means. A comparator is coupled to an output of the counter. A first divider is...
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7340631 |
Drift-tolerant sync pulse circuit in a sync pulse generator
A drift-tolerant sync generation circuit and sync generation method for a sync pulse generator operable in a clock synchronizer that effectuates data transfer between first circuitry disposed in a...
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7337347 |
Information processing system and method for timing adjustment
An elapsed cycle number during the predetermined period of the inputted clock source is counted using the clock reference signal as a yardstick, a frequency of the clock source is computed based on...
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7334152 |
Clock switching circuit
A clock switching circuit comprises: a composite clock generation circuit, which is to receive a first clock, a second clock, and a clock switching execution signal for switching between the first...
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7334148 |
Optimization of integrated circuit device I/O bus timing
The invention includes a method to adjust integrated circuit device I/O bus timing. In one embodiment, the method includes comparing an alignment between an edge of a first clock signal to a center...
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7325152 |
Synchronous signal generator
A synchronous signal generator is provided that contains a first and second counting and delay circuit, which both are in a subhierarchical position with respect to a reset signal...
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7321980 |
Software power control of circuit modules in a shared and distributed DMA system
A system-on-chip integrated circuit selectively gates clocks to individual modules corresponding to the state of a corresponding bit of a peripheral enable register. A reset circuit supplies a...
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7302601 |
Device and method for synchronizing an exchange of data with a remote member
A device is provided for synchronizing, on a reference clock signal, an exchange of data with a remote member. The device includes a main variable delay line controlled by a first processing unit...
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7293190 |
Noisy clock test method and apparatus
A clock filter for use in filtering an external clock signal to create an internal clock signal for use by an electronic device is provided. The clock filter receives the external clock signal and...
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7284139 |
Processor having real-time power conservation
A processor, comprising a monitor for, depending on the respective embodiment, measuring a relative amount of idle time, activity time, or idle time and activity time associated with the processor,...
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7278047 |
Providing different clock frequencies for different interfaces of a device
A method for operating a device (such as a printer) having a first interface (such as USB interface) connectable to a first computer and a second interface (such as an Ethernet interface)...
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7275171 |
Method and apparatus for programmable sampling clock edge selection
A method and apparatus for transferring data across a clock domain boundary is described. In one embodiment, a fixed relationship between a faster clock and a slower clock is maintained in the...
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7269754 |
Method and apparatus for flexible and programmable clock crossing control with dynamic compensation
A system and method for crossing clocks from a source clock to a destination clock is disclosed. In one embodiment, a source clock phase enable signal is used to enable a set of latch components to...
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7257727 |
Timer systems and methods
Systems and methods are disclosed for timer architectures. For example, in accordance with an embodiment of the present invention, a timer system includes a prescaler and one or more timer cells...
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7254729 |
Processing system and memory module having frequency selective memory
A memory module and an apparatus having a memory module for generating an internal clock synchronized to an external clock, the memory module being operated based on the internal clock as an...
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7243255 |
Design of instantaneously restartable clocks and their use such as in connecting clocked subsystems using clockless sequencing networks
Disclosed are, inter alia, instantaneously restartable clocks and their use. For example, instantaneously restartable clocks can be used to receive data from another independently clocked subsystem...
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7237216 |
Clock gating approach to accommodate infrequent additional processing latencies
A processor system has a first device, a clock control circuit and a processor. The first device receives a clock signal, runs a plurality of operations including a lengthy operation requiring more...
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7231537 |
Fast data access mode in a memory device
A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the...
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7219251 |
Programmable clock synchronizer
A programmable synchronizer system for effectuating data transfer across a clock boundary between a core clock domain and a bus clock domain, wherein the core clock domain is operable with a core...
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7216247 |
Methods and systems to reduce data skew in FIFOs
The disclosed invention provides methods and systems for writing and reading data in systems using multiple FIFO buffer elements. For each buffer element, a determination is made of when the rising...
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7194650 |
System and method for synchronizing multiple synchronizer controllers
A system and method for coordinating synchronizer controllers disposed in different clock domains, e.g., a core clock domain and a bus clock domain, wherein a clock synchronizer arrangement is...
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7181638 |
Method and apparatus for skewing data with respect to command on a DDR interface
An adjustable logic circuit includes a pulse filter and delay circuit, a state machine and combinational logic circuit, and a data strobe generation circuit. The pulse filter and delay circuit is...
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7171577 |
Methods and apparatus for a system clock divider
A power-saving clock divider scheme is cost-effective, flexible, jitterless, and allows the user to keep track of time. In general, the clock divider selectively operates in a normal mode and one...
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7155627 |
Memory system and data transmission method
A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory...
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