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8181056 |
Serial-connected memory system with output delay adjustment
Systems and methods for performing output delay adjustment are provided for application in serial-connected devices operating as slave devices. A master device provides a clock to the first slave...
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8181059 |
Inter-processor communication channel including power-down functionality
Apparatuses and methods are disclosed for implementing an inter-processor communication channel including power-down functionality. In one embodiment, the apparatus may comprise a first integrated...
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8176351 |
Sampling mechanism for data acquisition counters
One or more counter units of a data acquisition device used to perform sampling operations. Each of the counter units is configurable to operate in a selected one of a plurality of modes. During...
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8161313 |
Serial-connected memory system with duty cycle correction
Systems and methods for correcting clock duty cycle are provided for application in serial-connected devices operating as slave devices. A master device provides a clock to the first slave device,...
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8140882 |
Serial bus clock frequency calibration system and method thereof
A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device and a second frequency calibration device both to...
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8136161 |
3-prong security/reliability/real-time distributed architecture of information handling system
The present invention is directed to a distributed architecture of an information handling system, including a buried nucleus inaccessible for inspection without heroic means while the buried...
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8132040 |
Channel-to-channel deskew systems and methods
Systems and methods are disclosed herein to provide channel-to-channel skew control in accordance with one or more embodiments of the present invention. For example in accordance with an...
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RE43223 |
Dynamic memory management
In a method, system and apparatus for management of dynamic memory in battery-powered devices, information is stored in dynamic memory, such as SDRAM chips. Chip partitioning minimizes the number...
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8116321 |
System and method for routing asynchronous signals
A router, for routing at least one input signal to at least one output, comprises at least one input module and at least one output module. Each of the input and output modules includes at least...
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8103003 |
Method for setting communication parameters and communication device
A method for setting communication parameters in a plurality of communication devices includes setting communication parameters without an authentication process being performed for a second...
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8090971 |
Data recovery architecture (CDR) for low-voltage differential signaling (LVDS) video transceiver applications
The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is...
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8060771 |
Glitch-free clock suspend and resume circuit
Circuits and methods to provide a digital clock signal, which can be instantly halted without glitches and then resumes under control of an asynchronous suspend signal with whole width clock pulses...
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8046615 |
Microcomputer system with reduced power consumption
A sub-microcomputer having a sub-CPU and a power supply control section that controls the power supply to a main microcomputer is disposed in addition to the main microcomputer having a main CPU. A...
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8046731 |
Timer service computer program components
A method and apparatus for a timer service for program components. An embodiment of a method includes receiving a request for a timer for a program component. The method further includes...
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8042010 |
Two-phase clock-stalling technique for error detection and error correction
One embodiment of the present invention provides a system that augments a circuit design with a mechanism for detecting and correcting timing errors. This system first partitions the circuit into a...
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8037336 |
Spread spectrum clock generation
The present disclosure provides a spread spectrum clock generation system having a digitally controlled phase locked loop (PLL) and a digital frequency profile generator to create a near optimal...
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8024599 |
Bias and random delay cancellation
A system and method for digital communication wherein a host provides a host clock and a clockless device transmits to the host a bit stream synchronized according to the clock at a data rate that...
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8020022 |
Delay time control of memory controller
A memory control circuit has a write leveling function and controls read/write operations by supplying a clock signal to a plurality of memories through a clock signal line which is wired to the...
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8020027 |
Timing control in a specialized processing block
The tension between fmax and Tco in a specialized processing block of a programmable integrated circuit device can be reduced by providing variable delays on the clock inputs of the pipeline...
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8015428 |
Processing device and clock control method
A processing device comprises an interface and its control circuit for performing data transfer in synchronization with an external clock, an internal oscillator, and an interface and its control...
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7979732 |
Efficient utilization of a multi-source network of control logic to achieve timing closure in a clocked logic circuit
A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis...
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7973607 |
RTC circuit with time value adjustment
A technique involves the use of an electronic device having a real-time clock (RTC) circuit. In particular, the technique involves obtaining an RTC value from the RTC circuit. The RTC value is...
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7975161 |
Reducing CPU and bus power when running in power-save modes
A processing system includes a bus and a processor whose core is constrained to have one or more core clock signal frequencies no lower than a predetermined multiple of the lowest of one or more...
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7975164 |
DDR memory controller
A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is calibrated...
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7975163 |
Apparatus and method for masking a clock signal
A system and method are disclosed for masking a clock input from a clock line when the clock line is not being driven by a clock source. The clock mask is triggered by a clock cycle from the clock...
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7966512 |
Data processing device and mobile device
A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface...
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7937606 |
Shadow unit for shadowing circuit status
Generally, the present disclosure concerns systems and methods for shadowing status for a circuit with a shadow unit. In one aspect, a system comprises a first circuit in a first dynamic clock...
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7937605 |
Method of deskewing a differential signal and a system and circuit therefor
A high-definition multimedia interface (HDMI) receiver recovers high speed encoded data which are transmitted differentially over data channels of a lossy cable, along with a clock. Inter symbol...
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7936375 |
Image processor, imaging device, and image processing system use with image memory
An image processor for lowering data transfer speed. A JPEG compression circuit performs two-dimensional compression process on data output from a YCbCr conversion circuit to generate compressed...
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7930582 |
Image processing apparatus and method of transmitting reference clock
An engine unit and a control unit are connected via an interface. A power source supplies electric power to the interface. The engine unit is controlled based on a reference clock generated in the...
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7930581 |
Automation device
The invention relates to an automation device, with which a multiplicity of physically distributed functional units communicate with each other by means of a common transmission protocol. The...
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7925013 |
System for data encryption and decryption of digital data entering and leaving memory
A system is described for encryption and decryption of digital data prior to the digital data entering the memory of a digital device by generating a key, sub-key and combining the sub-key with...
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7912999 |
Buffering method and apparatus for processing digital communication signals
A buffering apparatus to process digital communication signals includes a plurality of buffers, a processing unit, and programmed memory. The programmed memory has instructions directing the...
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7904716 |
Processing device and processing method
A digital MFP carries out an authentication of an operator by a user ID and a password prior to usage of the digital MFP. The digital MFP requests from the operator an instruction as to whether or...
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7899145 |
Circuit, system, and method for multiplexing signals with reduced jitter
An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power...
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7895460 |
Serially connected processing elements having forward and reverse processing time intervals
Methods and apparatus provide a delayed clock signal to a plurality of serially connected processing elements, such as a bidirectional pipeline processor. The processing elements include forward...
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7890782 |
Dynamic power management in an execution unit using pipeline wave flow control
Power is conserved by dynamically applying clocks to execution units in a pipeline of a microprocessor. A clock to an execution unit is applied only when an instruction to the execution unit is...
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7886179 |
Method for adjusting working frequency of chip
A method for adjusting the working frequency of a chip is provided. The method detects a frequency adjustment range of a graphic chip when a system is booted. Then, an application program in full...
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7877623 |
Method and apparatus for providing symmetrical output data for a double data rate DRAM
An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a...
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7873857 |
Multi-component module fly-by output alignment arrangement and method
A method and multi-component electronic module device are provided that control the timing of output of data from a plurality of components on the multi-component module. One or more of the...
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7865709 |
Computer motherboard
The present invention discloses a computer motherboard, which comprises: at least one memory module slot, a flash memory, a central processing unit socket; wherein, the memory module slot is used...
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7865755 |
Clock frequency variation of a clocked current consumer
A frequency regulator for varying a clock frequency of a power-supplied consumer operated in a clocked manner, wherein the frequency regulator is implemented to perform an overall variation of the...
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7836326 |
Apparatus with variable pipeline stages via unification processing and cancellation
To satisfy a required processing speed and achieve the maximum power-saving effect in a microprocessor. A control value is calculated by performing proportional and integral processing on a...
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7827431 |
Memory card having memory device and host apparatus accessing memory card
A memory card includes a clock I/O circuit, a data I/O circuit, a delay element, and an adjustment value holding circuit. The clock input/output circuit receives a first clock from a host...
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7818528 |
System and method for asynchronous clock regeneration
The present invention is a method of asynchronous clock regeneration. The method includes synchronizing a first write pointer and a second write pointer, the first write pointer being an offline...
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7818603 |
Deriving accurate media position information
Various embodiments utilize different counters or clocks, working in concert, to smooth out position information that is derived for a rendering/capturing device. Specifically, in at least some...
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7809974 |
Circuit to reduce power supply fluctuations in high frequency/high power circuits
A circuit for transitioning clocking speeds, or frequencies, is provided. With this circuit, a clocking circuit providing a first clock signal at a first clock frequency is coupled to a counter. A...
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7809970 |
System and method for providing a high-speed message passing interface for barrier operations in a multi-tiered full-graph interconnect architecture
A method, computer program product, and system are provided performing a Message Passing Interface (MPI) job. A first processor chip receives a set of arrival signals from a set of processor chips...
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7792026 |
Method of calculating a time period to wait for missing data packets
A method of receiving data packets. In the method of receiving data packets, a determination is made as to whether a received data packet is received out of an expected order. If the determining...
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7752476 |
Fast transition from low-speed mode to high-speed mode in high-speed interfaces
Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable,...
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