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9021293 Methods for operating a memory interface circuit including calibration for CAS latency compensation in a plurality of byte lanes  
A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface...
9015267 Method for setting addresses of slave devices in communication network  
A method for setting addresses of slave devices in a communication network is provided. In the communication network, a master device identifies address-collided slave devices and requests the...
9015508 Semiconductor device and automobile control system  
Even after power-down, distinction between a transition from a PLL normal-oscillation state and a transition from a PLL self-oscillation is allowed. A semiconductor device includes a first region...
8984322 Device configured to switch a clock speed for multiple links running at different clock speeds and method for switching the clock speed  
A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality...
8972761 Systems and methods for idle clock insertion based power control  
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. In one particular...
8966309 Distribution of an incrementing count value  
Circuitry is disclosed that comprises: at least one element located within the circuitry and configured to hold an increasing count value; an encoder for receiving the increasing count value from...
8959382 Controlling communication of a clock signal to a peripheral  
A method of communicating in an electronic system or apparatus is disclosed. The method includes using a processor to communicate with a peripheral. The method further includes using the...
8924768 Inter-processor communication channel including power-down functionality  
Apparatuses and methods are disclosed for implementing an inter-processor communication channel including power-down functionality. In one embodiment, the apparatus may comprise a first integrated...
8909974 Data processing apparatus, data processing method and recording medium  
A data processing apparatus comprising: a gate unit connected to an input or an output of a processing unit and configured to cut off the data input and output; a control unit configured to...
8886957 Systems, methods, software, and components using tamper-proof real-time clock  
The write-access control line for an RTC is combined with a clear line for an RTC signature register, so that changes to the RTC will cause subsequent reads to return an invalidity flag.
8881233 Resource management via periodic distributed time  
Systems and methods for providing resource management in a distributed network are disclosed. A loose collection of devices in a network may not be aware of the power restrictions for other...
8843777 Modifying periodic signals produced by microcontroller  
Multiple modules are connected to a signal output module via first and second busses. Different commands may be transmitted on the two busses. Both busses may be hierarchically constructed so that...
8843778 Dynamically calibrated DDR memory controller  
A method for calibrating a DDR memory controller is described. The method provides an optimum delay for a core clock delay element to produce an optimum capture clock signal. The method issues a...
8839018 Programmable mechanism for optimizing a synchronous data bus  
An apparatus including a JTAG interface, synchronous bus optimizer, core clocks generator, synchronous strobe driver, and a DLL. The JTAG interface receives control information indicating a first...
8751852 Programmable mechanism for delayed synchronous data reception  
An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, and a...
8751851 Programmable mechanism for synchronous strobe advance  
An apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, a core clocks generator, and a synchronous strobe driver. The JTAG interface is configured to receive...
8751850 Optimized synchronous data reception mechanism  
An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network, a composite delay element, and delay-locked loops (DLLs). The...
8726062 Data recovery architecture (CDR) for low-voltage differential signaling (LVDS) video transceiver applications  
The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is...
8707081 Memory clock slowdown  
Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention...
8694670 Time synchronization of multiple time-based data streams with independent clocks  
Techniques are described for synchronizing multiple time-based data streams with independent clocks wherein relationships between clock rates of timing devices associated with the time-based data...
8665913 Communication device to obtain time information  
A communication device that is to be connected to a providing server for providing time information via a network is provided. The communication device includes a congestion-degree obtainer to...
8667320 Deriving accurate media position information  
Various embodiments utilize different counters or clocks, working in concert, to smooth out position information that is derived for a rendering/capturing device. Specifically, in at least some...
8661285 Dynamically calibrated DDR memory controller  
A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is typically...
8661284 Method and system to improve the operations of a registered memory module  
A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a...
8631266 Semiconductor memory device and method of controlling the same  
A method of tuning a phase of a clock signal includes performing data training on a plurality of data pins through which data are input and output, in synchronization with a data clock signal;...
8612786 Deep idle mode  
A deep idle mode for electronic devices is described, which provides significant power savings while allowing significantly shorter resumption times than experienced with a suspend mode. During...
8595537 DLL phase detection using advanced phase equalization  
A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is...
8566629 Information processing apparatus and method of operation of data transfer circuit  
An information processing apparatus transferring data between at least a plurality of processors through first and second routes running through first and second data transfer circuits, which...
8560877 Image processing apparatus and method of transmitting reference clock  
An engine unit and a control unit are connected via an interface. A power source supplies electric power to the interface. The engine unit is controlled based on a reference clock generated in the...
8527805 Inter-processor communication channel including power-down functionality  
Apparatuses and methods are disclosed for implementing an inter-processor communication channel including power-down functionality. In one embodiment, the apparatus may comprise a first integrated...
8527804 Architecture and method for eliminating store buffers in a DSP/processor with multiple memory accesses  
A method and apparatus for controlling system access to a memory that includes receiving first and second instructions, and evaluating whether both instructions can architecturally complete. When...
8522067 Variable latency interface for read/write channels  
A variable latency interface and method for managing variable latency. An apparatus includes a storage device controller and a read/write channel coupled to the storage device controller by a...
8516292 Method and apparatus for providing symmetrical output data for a double data rate DRAM  
An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a...
8514654 Storage apparatus, substrate, liquid container, system, and control method of the storage apparatus  
A storage apparatus including a nonvolatile storage section and a control section controlling the nonvolatile storage section, wherein the control section has a detection circuit detecting...
8504868 Computer system with synchronization/desynchronization controller  
A computer system includes a processor, a submodule connected to the processor, an external access monitor configured to monitor a data transfer between the processor and the submodule, and a...
8495327 Memory device synchronization  
A memory controller includes first and second output modules for driving first and second data, respectively, to be written to a memory device. The memory controller also includes a clock module...
8468286 Variable-frequency bus adapter, adapting method and system  
A variable-frequency bus adapter, a variable-frequency bus adapting method and a variable-frequency bus adapting system are provided. The method includes: generating a bus blocking indication...
8458429 Memory controller idle mode  
An apparatus and method for dynamically modifying one or more operating conditions of a memory controller in an electronic device. Operating conditions may comprise clock frequency and power,...
8438416 Function based dynamic power control  
A system and method for dynamic function based power control is disclosed. In one embodiment, a system includes a bridge unit having a memory controller and a communication hub coupled to the...
8429442 Deriving accurate media position information  
Various embodiments utilize different counters or clocks, working in concert, to smooth out position information that is derived for a rendering/capturing device. Specifically, in at least some...
8407510 DDR interface bus control  
Systems and techniques for improved bus control, which may be particularly useful for double data rate (DDR) data transfer. A circuit may include a clock transmitter in communication with a clock...
8407508 Serial bus clock frequency calibration system and method thereof  
A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device, a second frequency calibration device and a...
8397098 Method for countervailing clock skew and core logic circuit using the same  
A method for countervailing clock skew between a first clock signal and a second clock signal in a core logic circuit. The second clock signal is sampled based on the first clock signal in a...
8375239 Clock control signal generation circuit, clock selector, and data processing device  
Provided are a technique for high-speed switching between clock signals different in frequency, and a clock-control-signal-generation circuit which serves to generate a control signal for clock...
8365006 Preventing circumvention of function disablement in an information handling system  
For disabling a first function in an information handling system, a dynamic signal is disabled. The first function is inoperable in response to the dynamic signal being disabled. At least a second...
8352794 Control of clock gating  
Clock signal control circuitry is disclosed along with a method for switching a clock between modes and a computer program product. The clock signal control circuitry is for receiving a clock...
8347132 System and method for reducing processor power consumption  
A system and method for reducing active power in processors is disclosed. A method embodiment comprises the steps of determining when a particular logic block is inactive, determining the powered...
8326364 High resolution, low power design for CPRI/OBSAI latency measurement  
As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, timing circuits are used to calculate the “round trip” latency across...
8327180 Data processing device and mobile device  
A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface...
8321713 Fast data access mode in a memory device  
A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the...