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9043634 Methods, systems, apparatuses, and computer-readable media for waking a SLIMbus without toggle signal  
Arrangements for restarting data transmission on a serial low-power inter-chip media bus (SLIMbus) are presented. A clock signal may be provided in an active mode to a component communicatively...
9043633 Memory controller with transaction-queue-monitoring power mode circuitry  
An integrated-circuit memory controller outputs to a memory device a first signal in a first state to enable operation of synchronous data transmission and reception circuits within the memory...
9036760 Receiving apparatus and method for detecting the number of bits of the same value in a received bit stream  
An edge interval measuring block measures a first same-edge interval. A bit number detector detects the number of bits in the first same-edge interval based on reference bit length information and...
9037895 System and methods for silencing hardware backdoors  
Methods for preventing activation of hardware backdoors installed in a digital circuit, the digital circuit comprising one or more hardware units to be protected. A timer is repeatedly initiated...
9032223 Techniques to manage operational parameters for a processor  
Techniques to manage operational parameters for a processor are described. For instance, a method includes monitoring performance values representing physical characteristics for multiple...
9026834 Communication entity with timing generator coupled via a digital protocol to sample-driven further communication entity  
An embodiment of the invention provides a communication device (100) for processing data samples and comprises a communication entity (102) and a further communication entity (104) communicatively...
9026835 Computer system for configuring a clock  
The present invention relates to a computer system and a clock configuring method. The computer system comprises at least two nodes, wherein each of the at least two nodes includes a selecting...
9026833 Semiconductor device and method for fetching data  
In order to reduce occurrence of a fetching error of a digital signal, caused by a power-source noise, there is provided a semiconductor device provided with a switching circuit for executing a...
9021292 Method and system for asynchronous serial communication in a ring network by generating an oversampling clock using a fractional rate multiplier and sampling a received data bit sequence that includes voltage and temperature information in a battery management system  
Systems and methods are disclosed which relate to improving synchronization of clocks between a sender and a receiver communicating via an asynchronous serial interface. In a ring topology, a...
9021291 Synchronous network  
A network node of a synchronous network, wherein said network node comprises a timing circuit which recovers a reference clock from a reception signal received by said network node from an...
9015516 Storing event data and a time value in memory with an event logging module  
Example embodiments disclosed herein relate to storing event data and a time value in memory with an event logging module. Example embodiments of the event logging module include event command...
9015267 Method for setting addresses of slave devices in communication network  
A method for setting addresses of slave devices in a communication network is provided. In the communication network, a master device identifies address-collided slave devices and requests the...
9015517 Information processing apparatus and time-of-day control method  
In an information processing apparatus, a control unit includes a first clock device for providing the time of day. A physical domain includes a second clock device, and implements a logical...
9015515 Single wire serial interface  
A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock...
9009519 Timing control device and control method thereof  
Provided is a timing control device including: a storage unit that stores multiple pieces of timing control information including identification information and expected value data; a first...
8996906 Clock management block  
A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple...
8990605 Apparatus and method for read preamble disable  
A memory device is provided. The memory device includes a preamble disable memory and a memory controller. The preamble disable memory is arranged to store preamble disable data. The preamble...
8990607 Memory interface circuits including calibration for CAS latency compensation in a plurality of byte lanes  
A memory interface circuit for read operations is described. The circuit includes one or more controller circuits, one or more read data delay circuits for providing CAS latency compensation for...
8984322 Device configured to switch a clock speed for multiple links running at different clock speeds and method for switching the clock speed  
A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality...
8984324 Establishing clock speed for lengthy or non-compliant HDMI cables  
A method whereby the frequency of the clock of an internal bus of a sink of High Definition Multimedia Interface (HDMI) data is reduced, and possibly deep color mode of a sink deactivated, in...
8977885 Programmable logic device data rate booster for digital signal processing  
A programmable logic device is provided that includes: a programmable interconnect adapted to route input signals through the device at a system clock rate; and a digital signal processor (DSP)...
8972769 Data processing apparatus and control method for controlling clock frequency based on calculated frequency-to-response-time ratios  
A data processing apparatus includes: a plurality of processing units adapted to process data according to input operation clocks; and a control unit adapted to measure response times of the...
8964778 Communication control device and information processing apparatus  
A communication control device includes: a first processing unit that converts an electrical signal received by a communication channel into digital data and outputs the digital data, and in a...
8966309 Distribution of an incrementing count value  
Circuitry is disclosed that comprises: at least one element located within the circuitry and configured to hold an increasing count value; an encoder for receiving the increasing count value from...
8966299 Optimizing power usage by factoring processor architectural events to PMU  
A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time...
8959382 Controlling communication of a clock signal to a peripheral  
A method of communicating in an electronic system or apparatus is disclosed. The method includes using a processor to communicate with a peripheral. The method further includes using the...
8959214 Method, system, and storage medium for collecting SNMP bandwidth data  
Collecting bandwidth data includes producing master and slave text files in response to simultaneous collection of data samples from a network device by servers, generating a clean data file by...
8949652 Glitchless programmable clock shaper  
In one embodiment, a microprocessor includes one or more processing cores. At least one processing core includes a clock shaping circuit that is configured to receive a clock input signal. The...
8949648 System and method to overcome wander accumulation to achieve precision clock distribution over large networks  
A system and method for synchronizing clocks across a packet-switched network eliminates wander accumulation to enable precision clock distribution across a large network. In addition to standard...
8943352 Low power timing, configuring, and scheduling  
A device reduces its energy consumption using a relatively lower frequency and lower power secondary oscillator to maintain timing information when a higher frequency and higher power primary...
8943351 USB based synchronization and timing system  
A synchronization apparatus, comprising: a USB device having a USB microcontroller, circuitry for observing USB traffic, and circuitry for decoding from a USB data stream a periodic data structure...
8942337 Systems and methods for handling race conditions during data transfer in an implantable medical device  
The accuracy of data processing operations in implantable medical devices is improved through reductions in errors associated with data acquisition, reading, and transmission. In one embodiment,...
8935559 System and method for reducing crosstalk in on-chip networks using a contraflow interconnect and offset repeaters  
A data connector includes two different sets of wires that transport data between components of a computer system. A first set of wires transports data from a first component to a second...
8930741 Voltage regulator with drive override  
Techniques to enable voltage regulators to adjust for coming load changes are presented herein. In some embodiments, a functional block such as a microprocessor core having an associated clock...
8924764 Systems and methods for rate matching in networks utilizing a strobe counter  
Method and system for rate matching in networks is provided. The method includes setting a strobe counter of a network device equal to an initial value; and determining whether a current clock...
8924767 Minimizing the use of chip routing resources when using timestamped instrumentation data by transmitting the most significant bits of the timestamp in series and transmitting the least significant bits of the timestamp in parallel  
A timestamp generator generates a timestamp value having a predetermined number of most significant bits and a predetermined number of least significant bits. The least significant bits are...
8918669 Mesochronous signaling system with clock-stopped low power mode  
In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of...
8918666 Apparatus for synchronizing a data handover between a first and second clock domain through FIFO buffering  
An apparatus for synchronizing a data handover between a first clock domain and a second clock domain includes a calculator, a first-in-first-out storage, a synchronization pulse generator, a fill...
8914662 Implementing transparent clock by correcting time information carried in data using residence time information  
The present invention discloses a device and method for implementing a transparent clock. The device comprises: a clock module, a data identification module and a data correction module, wherein...
8909974 Data processing apparatus, data processing method and recording medium  
A data processing apparatus comprising: a gate unit connected to an input or an output of a processing unit and configured to cut off the data input and output; a control unit configured to...
8909973 Timer unit circuit having plurality of selectors and counter circuits that start counting in response to output of selectors  
A timer unit includes a first selector that receives a fixed value and a first enable signal, a second selector that receives the fixed value and a count cycle signal, a third selector that...
8909957 Dynamic voltage adjustment to computer system memory  
A system and method are provided wherein the voltage to a random access memory system may be automatically, dynamically adjusted without requiring an operating system to be restarted. In one...
8904223 Communication between domains of a processor operating on different clock signals  
Implementations of the present disclosure involve an apparatus and/or method for communicating between domains of a computing system, where at least one of the domains operates on a skipped clock...
8892861 Method and apparatus for establishing safe processor operating points  
A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more...
8892932 Image forming apparatus and control apparatus  
The present image forming apparatus includes a first control unit and a second control unit driven by built-in clock oscillators to realize the distributed control. The first control unit...
8886988 Method of calibrating signal skews in MIPI and related transmission system  
In calibration mode, a clock signal and a data signal are respectively transmitted via a clock lane and a data lane of an MIPI. A test clock signal is provided by adjusting the phase of the clock...
8880928 Multirate transmission system and method for parallel input data  
A multirate transmission system for transmitting parallel input data from a first location to a second location includes a transmitter portion and a receiver portion. The transmitter portion...
8881233 Resource management via periodic distributed time  
Systems and methods for providing resource management in a distributed network are disclosed. A loose collection of devices in a network may not be aware of the power restrictions for other...
8880929 Indirect clock measuring and media adjustment  
A method for indirectly measuring the clock rate of a media rendering subsystem, in a media rendering device that has a separate hardware clock for rendering the media, by using the rate at which...
8874169 Method for the configuration of a communication device as well as a communication device  
Among other things, a method is described for the configuration of a communication device (10) as well as a communication device (10). In this method, a communication link (20) is created from the...