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7620828 |
Dynamically changing PCI clocks
A method, apparatus and computer-usable medium are presented for dynamically selecting a clock signal used by a peripheral device that is coupled to a motherboard. When the motherboard is powered...
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7620788 |
Memory device sequencer and method supporting multiple memory device clock speeds
A sequence state matrix has a plurality of time slots for storing a plurality of memory device signals. The memory device signals are loaded into the matrix by a sequencer load unit, which loads...
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7619449 |
Method and apparatus for synchronous clock distribution to a plurality of destinations
Circuits, methods and systems are disclosed providing clock synchronization circuits for synchronized clock distribution for a plurality of devices in a semiconductor device. The clock...
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RE40990 |
Data transmission across asynchronous time domains using phase-shifted data packet
A method and apparatus is provided for transmitting multi-bit data across asynchronous time domains. In one embodiment, the apparatus includes a first delay circuit to generate a selector signal...
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7617409 |
System for checking clock-signal correspondence
A data processing system is provided having a clock signal comparator comprising a reference input port for receiving a reference clock signal and at least a further input port for receiving...
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7617339 |
Serial interface circuit for data transfer
A serial interface circuit includes a first circuit disposed in the core portion and connected to the CPU, and a second circuit disposed in the peripheral circuit and connected to the peripheral...
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7606952 |
Method for operating serial flash memory
A transmission method for a serial periphery interface (SPI) serial flash includes the steps of providing a first system clock signal and transmitting a plurality of data strings with each two bits...
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7606942 |
Method for input output expansion in an embedded system utilizing controlled transitions of first and second signals
A method for expanding input/output in an embedded system is described in which no additional strobes or enable lines are necessary from the host controller. By controlling the transitions of the...
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7603579 |
Semiconductor chip and semiconductor integrated circuit device for relaying a reference clock from one hard macro to another
A semiconductor chip has: a plurality of hard macros which operates based on a reference clock; and a clock pad through which the reference clock is supplied from the outside to one of the...
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7602744 |
Detection of a simultaneous occurrence of an event at a plurality of devices
The invention relates to a detection of a simultaneous occurrence of an event of a predetermined kind at a plurality of electronic devices. At least two devices detect the event and record at their...
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7600144 |
Data transmission error reduction via automatic data sampling timing adjustment
A data transmission error reduction circuit is formed including a delay circuit, a detection circuit and a control circuit. In one embodiment, the delay circuit includes n delay element and...
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7599459 |
Receiving apparatus, data transmission system and receiving method
A receiving apparatus receives data sequences, each of which includes plural data blocks, from plural transmission lines, respectively. The apparatus includes plural elastic buffers and a deskew...
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7596710 |
Synchronization circuit and method with transparent latches
A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second...
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7596669 |
Apparatus and method for managing memory in a network switch
The present invention is related to a method and apparatus for managing memory in a network switch, wherein the memory includes the steps of providing a memory, wherein the memory includes a...
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7594146 |
Apparatus, method, and program for correcting time of event trace data
A time correcting apparatus includes a data input section which inputs all event trace data generated for each event executed on computing devices and outputs the event trace data in order of...
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7590882 |
System, method and storage medium for bus calibration in a memory subsystem
A cascaded interconnect system with one or more memory modules, a memory controller and a memory bus that utilizes periodic recalibration. The memory modules and the memory controller are directly...
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7590881 |
Method and apparatus for controlling an upper layer in a protocol stack to delay timeouts
In a device communicating over a network, a proxy to delay timeout of an application on the device where the proxy is on a communications path between the application and the network, the proxy...
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7590880 |
Circuitry and method for detecting and protecting against over-clocking attacks
The present invention is directed to circuitry for detecting and protecting against over-clocking attacks on hardware modules. The circuitry preferably comprises a test signal, a delay path for...
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7590879 |
Clock edge de-skew
Circuits, methods, and apparatus for deskewing rising and falling edges of a clock signal. One embodiment of the present invention utilizes a delay element in a data path to adjust a data signal...
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7590026 |
Access to printing material container
The present invention provides a storage device that enables identification data to be readily rewritten and ensures normal completion of a data writing operation in a short time period. In the...
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7587622 |
Power management of components having clock processing circuits
A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to...
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7581132 |
System and method for configuring a microcontroller clock system
A method is provided for configuring a microcontroller clock system that includes a main oscillator, a phase locked loop, and a backup oscillator. According to the method, the main oscillator and...
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7581131 |
Method and system for balancing clock trees in a multi-voltage synchronous digital environment
A method for balancing clock trees in a multi-voltage synchronous digital environment is provided that includes generating a first source clock signal in a first voltage domain based on a first...
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7577863 |
Addressing type frequency counter circuit
An addressing type frequency counter circuit is disclosed, which receives a multiple parameter and a clock of addressing input from an external circuit, and uses a hardware address to perform the...
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7577861 |
Duty cycle rejecting serializing multiplexer for output data drivers
A method and apparatus is described herein for serializing input data streams into an output data stream. A first and second input data stream are sampled upon rising edges of a first and second...
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7577226 |
Clock recovery circuitry
Clock recovery circuitry for recovering a clock signal from a data signal is disclosed. The clock recovery circuitry comprises sampling unit ( 46 ) for sampling the data signal at a plurality of...
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7574618 |
Interface circuit
Noise removal and detection are performed for a signal VBUS in a detection portion in accordance with a low-frequency clock signal CLK generated by a CR oscillation circuit, and a detection signal...
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7574274 |
Method and system for synchronizing audio processing modules
Embodiments of the present invention provide an audio system having wholly independent audio processing modules. The audio system includes a plurality of audio processing modules, a clock manager,...
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7573932 |
Spread spectrum clock generator
A spread spectrum clock generator includes a non-volatile memory to store control codes corresponding to a predetermined delay. A delay circuit receives a control code having a predetermined number...
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7571342 |
Processor system, instruction sequence optimization device, and instruction sequence optimization program
To reduce power consumption of a processor system including a plurality of processors without degradation of the processing ability, a flag detecting section detects an assignment control flag and...
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7571341 |
Method and system for fast frequency switch for a power throttle in an integrated device
The ability to change from a first bus ratio to a second bus ratio without draining the transaction queues of a processor.
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7568118 |
Deterministic operation of an input/output interface
In one embodiment, the present invention includes a method for receiving data from a second device in a first device, forwarding the data from an input/output (I/O) clock domain to a system clock...
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7565564 |
Switching circuit and method thereof for dynamically switching host clock signals
A switching circuit located in a computer system is disclosed in the present invention. The switching circuit comprises a first phase-locked loop generating a first host clock signal, a second...
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7561582 |
Data reception device
A data reception device having a reception data buffer unit storing a plurality of packets contained in a data packet, a reception data amount measuring unit measuring the data amount stored in the...
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7558980 |
Systems and methods for the distribution of differential clock signals to a plurality of low impedance receivers
Systems and methods to distribute clock signals using a common bus. In one embodiment, a clock signal distribution system includes: a bus; a transmitter coupled to the bus to drive a clock signal...
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7558530 |
Device for generating a clock signal
A device for generating an output clock signal intended to time a digital processing circuit, said generating device receiving a first clock signal, characterized in that it comprises an oscillator...
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7555670 |
Clocking architecture using a bidirectional clock port
Embodiments of the invention are generally directed to systems, methods, and apparatuses for a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional...
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7555669 |
Timing vector program mechanism
Timing vectors are used to pass execution of time-dependent operations from firmware/software to a hardware component (e.g., a state machine). These vectors may be stored as a vector table in a...
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7555585 |
Optimized performance and power access to a shared resource in a multiclock frequency system on a chip application
A request from a first processor for access to a shared resource in a computing system is received, and access is provided to the shared resource by the first processor at a first clock frequency....
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7552353 |
Controlling circuit for automatically adjusting clock frequency of a central processing unit
A controlling circuit for automatically adjusting clock frequency of a CPU is provided. The controlling circuit includes: a current sensing circuit for converting a current signal of the CPU to a...
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7552252 |
Memory interface circuit and method
An interface circuit and method are described, in which the interface circuit includes a plurality of bi-directional buffers and logic, responsive to a read request from a system component,...
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7549075 |
System and method for adjusting execution frequency of a central processing unit
A method for adjusting execution frequency of a central processing unit (CPU) in an electronic apparatus is provided. The method includes the steps of: (a) obtaining a state of a CPU workload in...
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7546480 |
High speed bus with alignment, re-timing and buffer underflow/overflow detection enhancements
In a networked system in which high speed busses interconnect sources and destinations of data, systems for and methods of data alignment, data re-timing, and circular buffer underflow/overflow...
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7545896 |
Asynchronous multi-clock system
A system for controlling the transfer of a signal sequence in a first clock domain to a plurality of other clock domains. The system comprising: detecting circuitry for detecting receipt of the...
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7543172 |
Strobe masking in a signaling system having multiple clock domains
Systems and methods for masking strobe signals in strobe-based systems are provided below. These strobe-masking systems receive a strobe signal from a component operating under one clock domain and...
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7543094 |
Target readiness protocol for contiguous write
A method of performing contiguous write transactions on a processor bus according to an embodiment of the present invention includes detecting, by a bus agent, a request for a write cycle,...
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7539889 |
Media data synchronization in a wireless network
A method of keeping global time in a wireless network, the method comprising the steps of: using a first 802.11 chip set to read a Time Synchronization Function (TSF) to provide an initial time...
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7539793 |
Synchronized multichannel universal serial bus
The invention provides a method and apparatus for providing a synchronized multichannel universal serial bus, the method in one aspect comprising supplementing the signal channels in the USB...
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7536580 |
System and method for generating timer output corresponding to timer request from plurality of processes
The present invention relates to timer generation corresponding to a plurality of timer requests, etc. necessary for task processes of a CPU and achieves efficient timer generation. The present...
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7536570 |
Microcontroller unit (MCU) with suspend mode
A microcontroller unit having a suspend mode of operation includes a processing circuit for receiving digital information and processing said received digital information. Timing circuitry...
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