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7945805 Architecture for a physical interface of a high speed front side bus  
A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side...
7941687 Method and apparatus for digital I/O expander chip with multi-function timer cells  
A method and apparatus for digital I/O expander chip with multi-function timer cells have been disclosed. A series of match reload registers load a series of match registers which are driven by a...
7937607 Asynchronous data holding circuit  
An asynchronous data holding circuit including a source synchronizer which acquires an enable signal synchronized with a destination clock, in response to a rising or falling edge of the enable...
7937605 Method of deskewing a differential signal and a system and circuit therefor  
A high-definition multimedia interface (HDMI) receiver recovers high speed encoded data which are transmitted differentially over data channels of a lossy cable, along with a clock. Inter symbol...
7937608 Clock generating circuit and digital circuit system incorporating the same  
A digital circuit system includes: a register, for receiving and registering digital data; an operation unit, for operating and generating resulting data according to the digital data registered...
7936375 Image processor, imaging device, and image processing system use with image memory  
An image processor for lowering data transfer speed. A JPEG compression circuit performs two-dimensional compression process on data output from a YCbCr conversion circuit to generate compressed...
7937606 Shadow unit for shadowing circuit status  
Generally, the present disclosure concerns systems and methods for shadowing status for a circuit with a shadow unit. In one aspect, a system comprises a first circuit in a first dynamic clock...
7930581 Automation device  
The invention relates to an automation device, with which a multiplicity of physically distributed functional units communicate with each other by means of a common transmission protocol. The...
RE42293 System and method for optimizing clock speed generation in a computer  
The present invention relates to a method of reducing a clock speed of a host bus to extend battery life and its operating time when a battery is supplying electric energy for a portable computer....
7925013 System for data encryption and decryption of digital data entering and leaving memory  
A system is described for encryption and decryption of digital data prior to the digital data entering the memory of a digital device by generating a key, sub-key and combining the sub-key with...
7925912 Method and apparatus for fine edge control on integrated circuit outputs  
A device for adjusting the timing of at least one edge of an output pulse created in response to a reference pulse is disclosed. Such a device may include a first memory circuit having two or more...
7925813 Method of fabricating a portable computer apparatus with thermal enhancements and multiple power modes of operation  
A portable computer adapted for electrical connection to a docking station having multiple power modes of operation is described. The portable computer has one or more CPU chips which have at...
7921316 Cluster-wide system clock in a multi-tiered full-graph interconnect architecture  
Mechanisms for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the...
7921321 Automatic clock and data alignment  
A circuit is described for automatically adjusting a phase of an input register load clock to be synchronized with transitions of data bits forming an n-bit word. The circuit detects the first...
7921320 Single wire serial interface  
A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock...
7921319 Method and system for providing a deterministic virtual clock  
A method and system for providing a virtual clock on a computer by multiplying the number of instructions executed by the average instruction execution time. It is however not reliable to use this...
7921322 Optimize personalization conditions for electronic device transmission rates with increased transmitting frequency  
Systems and/or methods that facilitate expediently transmitting and programming data to an electronic device that contains nonvolatile memory are presented. A host component facilitates the...
7917794 Method for optimizing a DSP input clock using a comparing/analyzing circuit  
A method optimizes a DSP Input clock using a clock comparing/analyzing circuit. The method of the present invention enables PLD to select a delay function of the PLD and signals from a plurality...
7917793 Apparatus providing locally adaptive retiming pipeline with swing structure  
The present invention uses a swing structure to avoid using a clock period at a non-efficient execution time. The execution time is precisely controlled to enhance a performance of a processor...
7917799 Method and system for digital frequency clocking in processor cores  
Disclosed are a method of and system for digital frequency clocking in a processor core. At least one-processor core is provided, and that processor core has a clocking subsystem for generating an...
7917795 Digital circuit to measure and/or correct duty cycles  
A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However,...
7917796 Method and apparatus for the generation and control of clock signals  
Methods and apparatuses for the dynamic configuring of profiles used for the control of the frequency of clock signals. At least one embodiment of the present invention provides a means of...
7912999 Buffering method and apparatus for processing digital communication signals  
A buffering apparatus to process digital communication signals includes a plurality of buffers, a processing unit, and programmed memory. The programmed memory has instructions directing the...
7913102 Variable frequency clock output circuit and apparatus, motor driving apparatus, and image forming apparatus  
A variable frequency clock output circuit, comprising: a target value register which stores a target value corresponding to an arbitrarily set target frequency; an increase/decrease value register...
7908509 Method and apparatus for controlling an upper layer in a protocol stack to delay timeouts  
In a device communicating over a network, a proxy to delay timeout of an application on the device where the proxy is on a communications path between the application and the network, the proxy...
7908506 Memory card control chip  
The invention discloses a memory card control chip. The memory card control chip comprises a clock generator, a first memory card interface, and a control circuit. The clock generator generates a...
7908508 Low power method of responsively initiating fast response to a detected change of condition  
A voltage signal is monitored in comparison to another voltage signal by a differential amplifier. When the first voltage signal value drops below the second voltage signal value an output signal...
7904716 Processing device and processing method  
A digital MFP carries out an authentication of an operator by a user ID and a password prior to usage of the digital MFP. The digital MFP requests from the operator an instruction as to whether or...
7900079 Data capture window synchronizing method for generating data bit sequences and adjusting capture window on parallel data paths  
A self test function in the Memory Controller is utilized to generate unique and continuous data patterns for each of the words which are stored into two consecutive DRAM addresses in two spaced...
7900081 Microcomputer and control system having the same  
A microcomputer includes a main oscillator for generating and outputting a main clock signal, a sub oscillator for generating and outputting a sub clock signal, a central processing unit that...
7900078 Asynchronous conversion circuitry apparatus, systems, and methods  
Apparatus, systems, and methods operate to receive a sufficient number of asynchronous input tokens at the inputs of an asynchronous apparatus to conduct a specified processing operation, some of...
7895461 Clock shifting and prioritization system and method  
A clock shifting and prioritization method comprising adjusting a frequency for a plurality of clocks corresponding to a plurality of respective components of an electronic device based on a...
7890680 Physical layer device having a serdes pass through mode  
A physical layer device (PLD), comprising: a first serializer-deserializer (SERDES) device having a first parallel port; a second SERDES device having a second parallel port; a third SERDES device...
7890782 Dynamic power management in an execution unit using pipeline wave flow control  
Power is conserved by dynamically applying clocks to execution units in a pipeline of a microprocessor. A clock to an execution unit is applied only when an instruction to the execution unit is...
7886179 Method for adjusting working frequency of chip  
A method for adjusting the working frequency of a chip is provided. The method detects a frequency adjustment range of a graphic chip when a system is booted. Then, an application program in full...
7886175 Delaying one-shot signal objects  
A device may include a processor to execute a thread. The processor may be further configured to execute a set of wrappers that are called from within the thread to invoke a set of one-shot signal...
7882385 Reducing inefficiencies of multi-clock-domain interfaces using a modified latch bank  
A system and method for improving the performance and efficiency of multi-clock-domain data transmission interfaces. The data transmission interface may include a modified slave latch which...
7877623 Method and apparatus for providing symmetrical output data for a double data rate DRAM  
An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a...
7873857 Multi-component module fly-by output alignment arrangement and method  
A method and multi-component electronic module device are provided that control the timing of output of data from a plurality of components on the multi-component module. One or more of the...
7865759 Programmable clock control architecture for at-speed testing  
According to one exemplary embodiment, an N-stage programmable clock control architecture includes N flip-flops, where the N flip-flops are clocked by a primary clock source, such as a PLL. The...
7865755 Clock frequency variation of a clocked current consumer  
A frequency regulator for varying a clock frequency of a power-supplied consumer operated in a clocked manner, wherein the frequency regulator is implemented to perform an overall variation of the...
7865709 Computer motherboard  
The present invention discloses a computer motherboard, which comprises: at least one memory module slot, a flash memory, a central processing unit socket; wherein, the memory module slot is used...
7865749 Method and apparatus for dynamic system-level frequency scaling  
A method and apparatus for changing a clock frequency in a system (10) comprising a plurality of synchronous integrated circuit chips (12, 14, 16), and a circuit (20) for implementing the...
7856571 Method and system for communication employing dual slew rates  
A bus for implementation with a computer system, as well as a computer processing device capable of interacting with such a bus, and a method of communicating signals over a bus, are disclosed. In...
7849349 Reduced-delay clocked logic  
Delay in a clocked logic circuit is reduced by partially determining a next state of the clocked logic circuit based on a current state of the clocked logic circuit during a first portion of a...
7849339 Power-saving clocking technique  
A method and system for providing a clock signal having reduced power consumption is provided, called the hybrid clock system. The hybrid clock system uses a PLL for high-speed data transfers, but...
7849348 Programmable delay clock buffer  
A programmable delay clock buffer circuit, preferably implemented in a single IC, includes a clock circuit and a plurality of variable delay lines. The clock circuit receives an input clock and is...
7844848 Method and apparatus for managing remote display updates  
A method of transmitting encoded computer display images between computers over a nondeterministic network is disclosed. During a display session in which images are transmitted from a host to a...
7840825 Method for autonomous dynamic voltage and frequency scaling of microprocessors  
A method for autonomous dynamic voltage (v) and frequency (f) scaling (DVFS) of a microprocessor, wherein autonomous detection of phases of high microprocessor workload and prediction of their...
7840675 Multi node server system  
A server system has, in addition to extensibility of scale-out type of a braid server system, extensibility of scale-up type by making SMP coupling among nodes. Each node has a unit for SMP...