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8065553 Phase interpolator for a timing signal generating circuit  
A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for...
8060769 Duplexed field controller  
There is provided a duplexed field controller. The duplexed field controller includes: first and second control units between which a control authority is switchable; a first application clock...
8055932 Precision oscillator for an asynchronous transmission system  
A precision oscillator for an asynchronous transmission system. An integrated system on a chip with serial asynchronous communication capabilities includes processing circuitry for performing...
8050372 Clock-data recovery circuit, multi-port receiver including the same and associated methods  
A clock-data recovery circuit includes a plurality of input ports and a code generation circuit. The plurality of input ports generates sampling clock signals based on digital control codes and...
8051224 Method, system, and integrated chip for serial data transmission  
The invention provides a method for serial data transmission. First, a chip select signal is enabled to a device for serial data transmission. Data stored in a first buffer of a controller is then...
8046615 Microcomputer system with reduced power consumption  
A sub-microcomputer having a sub-CPU and a power supply control section that controls the power supply to a main microcomputer is disposed in addition to the main microcomputer having a main CPU....
8046623 Timing recovery apparatus and method thereof  
A multimedia processing system for processing a program stream containing a program clock reference information. The system comprises a clock generator, a timer, a modifier, a processing unit, a...
8046510 Physical layer device having a SERDES pass through mode  
A physical layer device (PLD), comprising: a first serializer-deserializer (SERDES) device having a first parallel port; a second SERDES device having a second parallel port; a third SERDES device...
8042010 Two-phase clock-stalling technique for error detection and error correction  
One embodiment of the present invention provides a system that augments a circuit design with a mechanism for detecting and correcting timing errors. This system first partitions the circuit into...
8041858 Method of clock distribution for operating an automation system  
A method of operating an automation system with a plurality of automation devices connected for communication with a central unit is provided. Each automation device handles communication in...
8041874 USB and ethernet controller combination device  
A USB-to-Ethernet controller with a USB hub may be integrated into a single integrated circuit (IC) USB-Ethernet Combination (UEC) device. The UEC may provide the end user with an Ethernet port,...
8041978 Method for ensuring synchronous presentation of additional data with audio data  
A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The...
8037336 Spread spectrum clock generation  
The present disclosure provides a spread spectrum clock generation system having a digitally controlled phase locked loop (PLL) and a digital frequency profile generator to create a near optimal...
8037339 Security device intended to be connected to a processing unit for an audio/video signal and process using such a device  
Example embodiments relate to a security device having two communication interfaces sharing at least one pin, each interface being capable of operating according to either of two predetermined...
8028187 Dual-mode communication apparatus and power management method thereof  
A dual-mode communication apparatus and a method thereof are provided. The dual-mode communication apparatus comprises a microprocessor, a first tick generator, a second tick generator, and an...
8024597 Signal phase verification for systems incorporating two synchronous clock domains  
The present invention implements a mechanism which enables zero-delay verification tools to detect clock domain crossing violations in device under test designs comprising two different clock...
8024598 Apparatus and method for clock generation with piecewise linear modulation  
An apparatus and method for generating a clock using piecewise linear modulation are provided. The apparatus includes: a modulation profile generator for outputting an M-bit digital profile...
8024599 Bias and random delay cancellation  
A system and method for digital communication wherein a host provides a host clock and a clockless device transmits to the host a bit stream synchronized according to the clock at a data rate that...
8020018 Circuit arrangement and method of operating a circuit arrangement  
A circuit arrangement is provided comprising a first partial circuit to receive a supply voltage, a second partial circuit to receive an output signal of the first partial circuit and a first...
8020026 Phase-aligning corrected and uncorrected clocks  
The present invention relates to providing a system clock signal that is based on either a first clock signal that is capable of being frequency-corrected or a second clock signal that is not...
8020023 Systems and methods for synchronizing operations among a plurality of independently clocked digital data processing devices without a voltage controlled crystal oscillator  
Exemplary systems and methods include a distribution device that maintains a clock rate and distributes a series of tasks to a group of execution devices. Each task has a plurality of samples per...
8015428 Processing device and clock control method  
A processing device comprises an interface and its control circuit for performing data transfer in synchronization with an external clock, an internal oscillator, and an interface and its control...
8015429 Clock and data recovery (CDR) method and apparatus  
Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method...
8015427 System and method for prioritization of clock rates in a multi-core processor  
A system and method for prioritization of clock rates in a multi-core processor is provided. Instruction arrival rates are measured during a time interval Ti−1 to Ti by a monitoring module either...
8006115 Central processing unit with multiple clock zones and operating method  
One embodiment of the invention comprises, in each clock zone of a central processing unit, at least one sensor that generates a power signal indicative of a power supply voltage within the clock...
8001412 Combined alignment scrambler function for elastic interface  
An interface alignment pattern for de-skewing data bits received on an elastic interface is disclosed. The interface alignment pattern is “busy” in that it has a high number of logic state...
8001410 Efficient clocking scheme for ultra high-speed systems  
There is provided a system for comparing the phase characteristics of three generated clock signals, each having a unique phase relationship with an original clock signal, with the original clock...
7996692 Information processing apparatus and semiconductor integrated circuit  
The information processing apparatus equipped with a microprocessor is provided. The information processing apparatus equipped with a microprocessor includes: an operation clock signal generator...
7995620 Method and data transmission system for transferring data between the data transmission system and a host processor of a participant in a data transmission system  
A method for transferring data between a data transmission system and a processor of a participant in the data transmission system. All components of the data transmission system are synchronized...
7996699 System and method for synchronizing multiple media devices  
Multiple media devices are synchronized in a multi-media system having a computer system, a plurality of media devices, and a display system. Each media device to be synchronized receives a...
7996704 Asynchronous first in first out interface and operation method thereof  
The invention provides an asynchronous first in first out (FIFO) interface and operation method wherein a read-out clock and a write-in clock of the asynchronous FIFO interface is asynchronous....
7996705 Signal bus, multilevel input interface and information processor  
A multilevel input interface device connected to a signal bus including one or more data lines that transmit an M-level signal and a clock line that transmits a transmission clock signal...
7987382 Method and apparatus for minimizing the influence of a digital sub-circuit on at least partially digital circuits  
One inventive aspect relates to a digital sub-circuit suitable for embedding in an at least partially digital circuit for minimizing the influence of another digital sub-circuit on the at least...
7984216 Method and system for a RFIC master  
Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one...
7984321 Data transfer control device and electronic instrument  
A data transfer control device includes an OUT-transfer transmitter circuit which transmits OUT data by driving a serial signal line, a clock-transfer transmitter circuit which transmits a clock...
7983374 Methods and systems for providing variable clock rates and data rates for a SERDES  
A method and apparatus for varying an output clock signal frequency to match the frequency of an output data signal frequency for a SERDES circuit while maintaining a constant input clock...
7984214 Data bus interface with interruptible clock  
In a data bus with asynchronous data transmission via a clock and a data line, the transmitted data are ascertained by sampling with a multiple of the data rate of the data bus. Sampling is done...
7983770 External ambient noise monitoring to adapt control of internal system noise sources  
An arrangement for controlling a system generated noise level such that the same is adapted to an actual ambient noise level of the system environment. Internal noise generators will thus not run...
7979732 Efficient utilization of a multi-source network of control logic to achieve timing closure in a clocked logic circuit  
A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis...
7975161 Reducing CPU and bus power when running in power-save modes  
A processing system includes a bus and a processor whose core is constrained to have one or more core clock signal frequencies no lower than a predetermined multiple of the lowest of one or more...
7975163 Apparatus and method for masking a clock signal  
A system and method are disclosed for masking a clock input from a clock line when the clock line is not being driven by a clock source. The clock mask is triggered by a clock cycle from the clock...
7971087 Dynamic clock control circuit and method  
A variable clock control information generator receives graphics engine activity data relating to the operating level of a graphics engine, and memory activity data relating to an activity level...
7966512 Data processing device and mobile device  
A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface...
7958383 Computer system with adjustable data transmission rate  
A computer system has an adjustable data transmission rate between a CPU and a core logic chip thereof. In the computer system, the CPU has a power state adjustable in response to a power...
7953998 Clock generation circuit and semiconductor memory apparatus having the same  
A clock generation circuit for a semiconductor memory apparatus includes an internal clock generation unit that receives a clock and generates an internal clock, and a clock selection unit that...
7954001 Nibble de-skew method, apparatus, and system  
De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.
7953999 Semiconductor integrated circuit device and method of operating the same  
A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a central processing unit (CPU) configured to output first control signals in response...
7949080 Phase adjusting function evaluating method, transmission margin measuring method, information processing apparatus and computer readable information recording medium  
A phase amount added to a clock signal or a plurality of data signals for adjusting a phase relationship therebetween in a reception apparatus is changed, and, a result of the phase adjusting...
7945804 Methods and systems for digitally controlled multi-frequency clocking of multi-core processors  
A method and system for digitally controlled multi-frequency clocking are provided. The method includes receiving a system reference oscillator clock frequency at a microprocessor including...
7945806 Data processing apparatus and method for controlling a transfer of payload data over a communication channel  
A data processing apparatus has initiator circuitry for initiating a transfer of payload data in a first clock cycle, and recipient circuitry for receiving the payload data in a later clock cycle....