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8166316 Single interface access to multiple bandwidth and power memory zones  
In an embodiment, a system comprises a first memory module interface unit (MMIU) configured to couple to a first one or more memory modules, and a second MMIU configured to couple to a second one...
8165199 Method and apparatus for on-chip voltage controlled oscillator function  
This invention uses a flying adder frequency synthesis circuit to provide the required frequency adjustments to accommodate the varying encoding density of a MPEG2 video data stream. This...
8161195 Adaptable management in sync engines  
Synchronization of two or more items can be optimized through the use of parallel execution of synchronization tasks and adaptable processing that monitors and adjusts for system loading. Two or...
8161204 Embedded clock recovery  
Systems and methods for synchronizing a source and sink device are disclosed. A sink device can efficiently determine the source data rate even in cases where the sink device is not directly...
8161212 Data operations across parallel non-volatile input/output devices  
An embodiment of a system for implementing parallel usage of a plurality of non-volatile input/output (I/O) devices can include an interface configured to receive, from a source, a source request...
8161314 Method and system for analog frequency clocking in processor cores  
A method of and system for frequency clocking in a processor core are disclosed. In this system, at least one processor core is provided, and that at least one processor core has a clocking...
8161311 Apparatus and method for redundant and spread spectrum clocking  
An apparatus and method for fault-tolerant and spread spectrum clocking. In one embodiment a master clock synthesizer circuit generates an output clock signal of varying frequency within a...
8156272 Multiple communication channels on MMC or SD CMD line  
The claimed subject matter can provide an architecture that interfaces a single slave device such as a UICC smartcard with multiple host controllers. For example, a secondary host can be...
8156365 Data reception apparatus  
A data reception apparatus is disclosed. The data reception apparatus includes a strobe extractor for receiving a transmission signal and extracting a strobe signal from the transmission signal,...
8151132 Memory register having an integrated delay-locked loop  
A memory device is provided. The memory device includes a plurality of memory chips coupled in series, and a register serially coupled to the memory chips. The register includes an integrated...
8151134 SPI devices and method for transferring data between the SPI devices  
A method for transferring data between a serial peripheral interface (SPI) master device and an SPI slave device generates a first clock signal for the SPI master device and a second clock signal...
8151133 Method for calibrating read operations in a memory system  
A method of calibrating read operations in a memory system is disclosed. The method involves placing a memory controller in a calibration mode, and performing a series of dummy read operations....
8151131 Signal synchronization method and signal synchronization circuit  
There is provided a signal synchronization method of performing signal synchronization between a device which operates in synchronization with a first clock signal and a processor which operates...
8149979 Method and apparatus for handling of clock information in serial link ports  
A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a...
8145247 Clock synchronization for a wireless communications system  
Clock synchronization for a wireless communication system is described. The communication system utilizes a server with a radio coupled to receive a radio frequency (RF) signal and a clock...
8144689 Controlling asynchronous clock domains to perform synchronous operations  
A mechanism for controlling asynchronous clock domains to perform synchronous operations is provided. With the mechanism, when a synchronous operation is to be performed on a chip, the latches of...
8140881 Circuitry and method for detection of network node aging in communication networks  
The network node includes a local crystal oscillator for providing a time reference derived from the clock signal produced by the local crystal oscillator, a reset stage for resetting the network...
8140882 Serial bus clock frequency calibration system and method thereof  
A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device and a second frequency calibration device both...
8139433 Memory device control for self-refresh mode  
To ensure that a memory device operates in self-refresh mode, the memory controller includes (1) a normal-mode output buffer for driving a clock enable signal CKE onto the memory device's CKE...
8140885 Accounting for microprocessor resource consumption  
Techniques for accounting microprocessor resource consumption. The present invention provides an automatic method to timely determine the current microprocessor clock frequency. Information...
8134391 Semiconductor devices with signal synchronization circuits  
Semiconductor devices are disclosed providing synchronization circuits for synchronized signal distribution for a plurality of devices in a semiconductor device. The synchronization apparatus...
8132036 Reducing latency in data transfer between asynchronous clock domains  
A method and an interfacing circuit are disclosed for transmitting data between a first clock domain operating at a first clock frequency C1 and a second clock domain operating at a second clock...
8132040 Channel-to-channel deskew systems and methods  
Systems and methods are disclosed herein to provide channel-to-channel skew control in accordance with one or more embodiments of the present invention. For example in accordance with an...
8131989 Method and apparatus for establishing safe processor operating points  
A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more...
8132041 Method and apparatus for generating or utilizing one or more cycle-swallowed clock signals  
An electronic device is provided for generating or utilizing one or more cycle-swallowed clock signals derived based on one or more first clock signals. The device includes a module configured to...
8132039 Techniques for generating clock signals using counters  
The circuit, typically a delay-locked loop, comprises a phase detector, a first counter, a second counter, and a comparator. The phase detector compares a phase of a first clock signal with a...
8131882 Method for input output expansion in an embedded system utilizing controlled transitions of first and second signals  
A method for expanding input/output in an embedded system is described in which no additional strobes or enable lines are necessary from the host controller. By controlling the transitions of the...
8122279 Multiphase clocking systems with ring bus architecture  
Systems and methods for transferring data using a ring bus architecture in a system that implements multi-phase clocking. In one embodiment, the system is a multiprocessor having multiple...
8122258 System and method for secure operating system boot  
There is provided a method for operating a basic input/output system (BIOS) of a pay-as-you go computer system. In one example embodiment, the method includes periodically resetting a watchdog...
8122277 Clock distribution chip  
In one embodiment, a clock distribution chip includes a clock input adapted to receive an input clock signal, clock dividers each adapted to receive a clock signal based on the first input clock...
8117483 Method to calibrate start values for write leveling in a memory system  
A memory controller performs a read test for each of a plurality of memory devices to generate a read delay time of each memory device. There is a prime memory device and a subset of memory...
8117478 Optimizing power usage by processor cores based on architectural events  
A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time...
8112654 Method and an apparatus for providing timing signals to a number of circuits, and integrated circuit and a node  
A method of providing or transporting a timing signal between a number of circuits, electrical or optical, where each circuit is fed by a node. The nodes forward timing signals between each other,...
8112656 Clock distribution chip  
In one embodiment, a clock distribution chip includes a first clock input adapted to receive a first single-ended input clock signal, a second clock input adapted to receive a second single-ended...
8111092 Register with process, supply voltage and temperature variation independent propagation delay path  
A digital data register is disclosed that provides setup and hold timing on the pre-register side, clock centering on the post-register side, and constant propagation delay time over variations in...
8111706 Premises gateway device  
In a premises gateway device that performs encryption or decryption under the IPsec, the throughput of a processor is varied depending on a type of data to be treated in order to realize reduction...
8103003 Method for setting communication parameters and communication device  
A method for setting communication parameters in a plurality of communication devices includes setting communication parameters without an authentication process being performed for a second...
8099619 Voltage regulator with drive override  
Techniques to enable voltage regulators to adjust for coming load changes are presented herein. In some embodiments, a functional block such as a microprocessor core having an associated clock...
8098784 Systems, methods and computer program products for high speed data transfer using a plurality of external clock signals  
A method for capturing data includes receiving a plurality of external clock signals including a first external clock signal and a second external clock signal. Each external clock signal has a...
8099618 Methods and devices for treating and processing data  
A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The...
8099621 Data reception apparatus and microcomputer having the same  
A data reception apparatus includes: an oscillation circuit that multiplies or divides an oscillation signal from a CR oscillator based on a cycle setting value, and outputs a clock signal...
8099537 Method, device, and system for transmitting data fragments over multiple transmission lines and techniques for stopping data transmission  
It is an object of the invention to inhibit a drop in the data transmission efficiency due to the transmission of an interrupt signal. The invention provides a signal transmission method that is...
8090971 Data recovery architecture (CDR) for low-voltage differential signaling (LVDS) video transceiver applications  
The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is...
8086892 Microcode configurable frequency clock  
A microcode configurable frequency clock that may be used to control the speed of high speed comparison in an operational optical transceiver. The frequency clock includes a memory and a logic...
8086890 Virtual machine monitor, virtual machine system and clock distribution method thereof  
A virtual machine monitor, a virtual machine system and a clock distribution method thereof. The clock distribution method includes: distributing real clock resource to a Guest Operation System...
8086891 Power management of components having clock processing circuits  
A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to...
8082462 Direct synthesis of audio clock from a video clock via phase interpolation of a dithered pulse  
An embodiment of the invention relates to a clock signal generator and a related method to produce a clock signal that is a rational but non-integer submultiple of a reference clock signal by...
8078999 Structure for implementing speculative clock gating of digital logic circuits  
A design structure embodied in a non-transitory machine readable medium used in a design process includes an apparatus for implementing speculative clock gating of digital logic circuits,...
8078899 Asynchronous conversion circuitry apparatus, systems, and methods  
Apparatus, systems, and methods operate to receive a sufficient number of asynchronous input tokens at the inputs of an asynchronous apparatus to conduct a specified processing operation, some of...
8074093 Method and system for optimizing the completion of computing operations  
Computer software that manages the amount of power provided to a processing unit for a specific process task, optimizing the processing speed of that specific task without overheating the...