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8271821 Flexible RAM clock enable  
A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic...
8271827 Memory system with extended memory density capability  
A system including a central processing unit, a first memory channel being configured to couple the central processing unit to a first semiconductor memory unit, wherein the first memory channel...
8271770 Computer motherboard with automatically adjusted hardware parameter value  
A computer motherboard with automatically adjusted hardware parameter values restarts automatically and proceeds with overclocking or power-saving operation in case the computer motherboard hangs...
8271823 DLL phase detection using advanced phase equalization  
A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is...
8266471 Memory device including a memory block having a fixed latency data output  
A memory block includes a memory circuit and a clock generation unit. The memory circuit may output read data in response to being clocked by a clock signal having a selectable delay that may be...
8266360 I2C-bus interface with parallel operational mode  
An electronic circuit has an interface for an I2C-bus. The interface comprises a first node for a clock line of the I2C-bus; a second node for a data line of the I2C-bus; and an I2C-bus controller...
8266469 Clock controlling apparatus of computer system and applications thereof  
A clock controlling apparatus of a computer system used to tuning a clock frequency of a specific electronic device disposed on a motherboard and the application thereof are disclosed, wherein the...
8266468 Integrated circuit with interpolation to avoid harmonic interference  
An integrated circuit (IC) includes a clock circuit, a processing module, and processing circuitry. The clock circuit is coupled to produce a digital clock signal. The processing module is coupled...
8266470 Clock generating device, method thereof and computer system using the same  
A clock generating device, method thereof and a computer system using the same are provided. The clock generating device includes a PLL module and a tuning module. The PLL module receives a...
8261120 Clock integrated circuit  
The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more...
8250341 Pipeline accelerator having multiple pipeline units and related computing machine and method  
A pipeline accelerator includes a bus and a plurality of pipeline units, each unit coupled to the bus and including at least one respective hardwired-pipeline circuit. By including a plurality of...
8250399 Method and apparatus for clock wander compensation  
Aspects of the disclosure provide a network device. The network device includes a first port coupled to a first device to communicate with the first device, and a clock wander compensation module....
8250394 Varying the number of generated clock signals and selecting a clock signal in response to a change in memory fill level  
A system and method provide adaptive frequency scaling for predicting the load on a processing unit and dynamically changing its clock frequency while keeping the synchronization with other...
8245074 Clock integrated circuit  
The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more...
8245075 Overclocking CPU with stepwise increase in frequency by BIOS gaining control upon interrupt generated at predetermined intervals  
A method for overclocking a central processing unit (CPU) of a computer motherboard is disclosed. Step A is to set a second frequency of front side bus (FSB) by an operating interface of BIOS....
8245073 Method and apparatus synchronizing integrated circuit clocks  
Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin...
8239702 One global precise time and one maximum transmission time  
Method of controlling a wind power system including a plurality of system elements, the wind power system including a plurality of data processors distributed in the system elements, the method...
8239704 Global clock via embedded spanning tree  
In some embodiments, the present invention relates to a method of maintaining a global clock within a multiprocessor system having a plurality of nodes that are connected in a network via links. A...
8234514 Method and apparatus for resolving clock management issues in emulation involving both interpreted and translated code  
Methods and systems for resolving clock management issues in emulation of a target system on a host system are disclosed. A first set of code instructions of a target program is emulated to...
8228747 Delay adjustment device, semiconductor device and delay adjustment method  
Provided is a delay adjustment device that contributes to downsizing the circuit that adjusts a flight time. The delay adjustment device is connected to a memory, and adjusts a timing to retrieve...
8225063 Synchronous dynamic random access memory interface and method  
A memory interface allows access to SDRAM by receiving a column address for a data read or write of a burst of data units. Each data unit in the burst has an expected bit size. The interface...
8225252 Systems, methods, apparatus and computer readable mediums for use in association with systems having interference  
In some embodiments, a method includes characterizing a plurality of channels, each of the plurality of channels being a channel between a location and a respective one of the plurality of...
8223910 Method and device for frame synchronization  
A device and a method for frame synchronization, the method includes providing a high frequency clock signal over a clock line during a transmission of information over a data line connected to a...
8219847 Arithmetic unit and arithmetic processing method for operating with higher and lower clock frequencies  
There is a need for providing a battery-less integrated circuit (IC) card capable of operating in accordance with a contact usage or a non-contact usage, preventing coprocessor throughput from...
8219845 Timer service uses a single timer function to perform timing services for both relative and absolute timers  
A timer service uses a single timer function to perform timing services for both relative and absolute timers. The first timers from a sorted array of absolute timers and relative timers are used...
8214668 Synchronizing circuit  
A synchronizing circuit includes an internal partial power supply interruption circuit section which can be subjected to a power supply interruption and includes a data transmission register...
8214563 Host computer, computer terminal, and card access method  
According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received...
8209563 Strategy to verify asynchronous links across chips  
Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over...
8209560 Transmission system where a first device generates information for controlling transmission and latch timing for a second device  
To provide a semiconductor device including a data input circuit and a data output circuit connected to a plurality of data input/output terminals, where at least one of the data input circuit and...
8209562 Double data rate converter circuit includes a delay locked loop for providing the plurality of clock phase signals  
In a memory interface, a delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a...
8205111 Communicating via an in-die interconnect  
In one embodiment, the present invention includes a method for writing data from a writer coupled to a reader via an in-die interconnect into a queue entry according to a first clock of the...
8201014 System and method for decoding an audio signal  
A system and method are provided for decoding an audio signal. In one embodiment, a first pulse is identified with a predetermined relative duration with respect to a second pulse. A sampling...
8201015 Control card circuit and method for selecting a synchronization source among a plurality of line card circuits  
A method and apparatus for handling, maintaining, and controlling network synchronization information emanating from a plurality of line card circuits is described. The technique described may be...
8195975 Semiconductor integrated circuit device and clock control method  
A plurality of operation units connected in a pipeline structure performs an operation processing on data. A process control unit operates in synchronization with a system clock signal and...
8190943 Systolic merge sorter  
A sorter system includes a clock continuously generating a series of clock signals, a systolic array circuit, and control circuitry in communication with serial access memory that stores data...
8190944 Device configured to switch a clock speed for multiple links running at different clock speeds and method for switching the clock speed  
A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality...
8185771 Clock generation for memory access without a local oscillator  
A method of accessing electronic memory is provided in electronic circuits where it is desired to lower power consumption and hence there is no active oscillator at the time when access to data...
8185957 Peripheral device  
A method for an impaired user to control a peripheral device including receiving key-value pair input from the user, determining whether the received input is valid and executing a job generated...
8181058 Clock-data-recovery technique for high-speed links  
A receiver circuit is described. In the receiver circuit, an analog-to-digital converter (ADC) generates first samples of a data signal based on a first clock signal, and a clock-data-recovery...
8176353 Method for the data transfer between at least two clock domains  
The invention describes a method for transferring data between a first clock domain having a first clock rate (CLK1) and at least one additional clock domain having a second clock rate (CLK2),...
8176351 Sampling mechanism for data acquisition counters  
One or more counter units of a data acquisition device used to perform sampling operations. Each of the counter units is configurable to operate in a selected one of a plurality of modes. During...
8176352 Clock domain data transfer device and methods thereof  
Two clock domains of a data processing device are each synchronized with a different clock signal. The clock signals are generated by clock generation logic. The clock generation logic also...
8176354 Wave pipeline with selectively opaque register stages  
A selectively synchronous wave pipeline segment and an integrated circuit (IC) including the segment. The segment includes a normally opaque input stage and output stage and multiple internal...
8171333 Sub-beam forming transmitter circuitry for ultrasound system  
Multi-channel pulser driver circuitry for a sub-beam forming transmitter of an ultrasound system in which sub-beam signals are formed by delaying sub-beam pulse pattern data in accordance with...
8171334 Apparatus and method to interface two different clock domains  
A gearbox is placed between two clock domains to allow data to be transferred from one domain to the other. Although the two domains may operate at the same clock frequency, typically one domain...
8171336 Method for protecting a secured real time clock module and a device having protection capabilities  
A method for protecting a secured real time clock module, the method includes: locking multiple input ports of the secured real time clock module if the multiple input ports of the secured real...
8171332 Integrated circuit with reduced electromagnetic interference induced by memory access and method for the same  
The invention provides an integrated circuit with reduced electromagnetic interference induced by memory access. The integrated circuit includes a random code generator, a request receiver and a...
8171320 Information processing apparatus, operation control method and operation control program storage medium  
An information processing apparatus having a processing circuit to execute a program by operating at a set operating frequency, including: a measuring section that measures an elapsed time from...
8171335 Clock timing calibration circuit and clock timing calibration method for calibrating phase difference between different clock signals and related analog-to-digital conversion system using the same  
A clock timing calibration circuit includes a clock timing adjusting unit and a calibration control unit. The clock timing adjusting unit is for receiving an incoming reference clock signal and...
8166216 Floating frame timing circuits for network devices  
A networking device includes a network port configured to receive a message from a remote networking device. The network port includes a detector configured to detect reception of the message. A...