Sign up


Match Document Document Title
8719616 Method for encoder frequency-shift compensation  
A method for encoder frequency-shift compensation includes determining frequency values of an input encoder signal, determining repeatable frequency-shifts of the frequency values and generating a...
8713345 Apparatus with a local timing circuit that generates a multi-phase timing signal for a digital signal processing circuit  
A local timing circuit receives a reference timing signal and generates a multi-phase timing signal for output to a digital signal processing circuit.
8713221 Rate controlled first in first out (FIFO) queues for clock domain crossing  
First in, first out (FIFO) queues may be used to transfer data between a producer clock domain and a number of consumer clock domains. In one implementation, a control component for the FIFO...
8713347 Apparatus and method for masking a clock signal  
A system and method are disclosed for masking a clock input from a clock line when the clock line is not being driven by a clock source. The clock mask is triggered by a clock cycle from the clock...
8704805 System and method for handling image data transfer in a display driver  
In a display driver, image data are assembled with synchronization information to form a stream of digital data. The stream of digital data is transmitted from a timing controller to a data driver...
8707081 Memory clock slowdown  
Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention...
8707077 Method and apparatus for time synchronisation in wireless networks  
A wireless media distribution system is provided comprising an access point (6) for broadcasting media and a plurality of stations (2) for reception and playback of media. Each station is...
8700944 Programmable drive strength in memory signaling  
Embodiments of the invention relate to programmable data register circuits and programmable clock generation circuits For example, some embodiments include a buffer circuit for receiving input...
8700933 Optimizing power usage by factoring processor architectural events to PMU  
A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time...
8689037 System and method for asynchronously and independently controlling core clocks in a multicore central processing unit  
A method of controlling core clocks in a multicore central processing unit is disclosed and may include executing a zeroth dynamic clock and voltage scaling (DCVS) algorithm on a zeroth core and...
8677053 Nonvolatile memory device and method for operating the same  
A nonvolatile memory device includes a selecting unit configured to select one of a read data or a program signal indicating a program period, an output unit configured to output an output signal...
8671305 Techniques for adjusting periodic signals based on data detection  
A circuit includes a phase detector circuit, a phase frequency detector circuit, a data detection circuit, a multiplexer circuit, and a clock signal generation circuit. The phase detector circuit...
8667319 System and method for clock control for power-state transitions  
Clock management is implemented using a variety of systems, devices and methods. According to one embodiment a clock transitioning circuit arrangement (104) is implemented for receiving data from...
8667320 Deriving accurate media position information  
Various embodiments utilize different counters or clocks, working in concert, to smooth out position information that is derived for a rendering/capturing device. Specifically, in at least some...
8667317 Circuitry including an RF front end circuit  
The present disclosure relates to RF front-end (RFFE) circuitry that includes multiple RFFE circuits, each of which may be provided by a separate integrated circuit (IC), front-end module, or...
8667318 Method and apparatus for wireless clock regeneration  
Methods and systems for operating a wireless clock system for multimedia datastream transmission and display. Source clock frames are compared with a reference clock frames and the clock...
8656150 Computer system with overclocking function involves setting time parameter of memory controller  
An overclocking method applied to a computer system includes the following steps: setting a first operating voltage and a first clock rate; generating a first control signal to a power supply and...
8656205 Generating reference clocks in USB device by selecting control signal to oscillator form plural calibration units  
A USB device with a clock calibration function and a method for calibrating reference clocks of a USB device are provided. A USB 2.0 initial calibration is performed on the USB device in order to...
8656204 Security device meant to be connected to a processing unit for audio/video signal and method using such a device  
Example embodiments relate to a security device having two communication interfaces sharing at least one pin, each interface being capable of operating according to either of two predetermined...
8650424 Method and apparatus to control power consumption of a plurality of processor cores  
For one disclosed embodiment, a plurality of processor cores of a multicore processor may be operated at variable performance levels. One processor core may operate at a performance level...
8635487 Memory interface having extended strobe burst for write timing calibration  
Methods and systems for calibrating parameters for communication between a controller and a memory device. A memory controller may be configured to calibrate one or more of the write latency...
8631266 Semiconductor memory device and method of controlling the same  
A method of tuning a phase of a clock signal includes performing data training on a plurality of data pins through which data are input and output, in synchronization with a data clock signal;...
8626966 Embedded clock recovery  
Systems and methods and computer program products are disclosed to determine the source data rate even in cases where the sink device is not directly coupled to the source device. A method...
8621109 Adaptable management in sync engines  
Synchronization of two or more items can be optimized through the use of parallel execution of synchronization tasks and adaptable processing that monitors and adjusts for system loading. Two or...
8621253 Processor boost based on user interface demand  
A method and system for boosting a clock frequency for a processor in a mobile device based on user interface (UI) demand are described. In response to a user interaction through a UI in the...
8612795 Segmented clock network for transceiver array  
One embodiment relates to a clocking network interconnecting an array of transceivers. The clocking network includes first and second series of multiplexers, each multiplexer in the first and...
8612786 Deep idle mode  
A deep idle mode for electronic devices is described, which provides significant power savings while allowing significantly shorter resumption times than experienced with a suspend mode. During...
8599642 Port enable signal generation for gating a memory array device output  
A method of generating a dynamic port enable signal for gating memory array data to an output node includes generating a programmable leading edge clock signal derivation of an input dynamic clock...
8601297 Systems and methods for energy proportional multiprocessor networks  
Energy proportional solutions are provided for computer networks such as datacenters. Congestion sensing heuristics are used to adaptively route traffic across links. Traffic intensity is sensed...
8595537 DLL phase detection using advanced phase equalization  
A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is...
8595527 Method of managing power of multi-core processor, recording medium storing program for performing the same, and multi-core processor system  
Provided are a method of managing power of a multi-core processor, a recording medium storing a program for performing the method, and a multi-core processor system. The method of managing power...
8594575 Shifted channel characteristics for mitigating co-channel interference  
Methods and apparatuses for minimizing co-channel interference in communications systems are disclosed. A method in accordance with the present invention comprises shifting a characteristic of the...
8595540 Rendering a content stream based on a digital clock generated based on timing information  
Systems, methods, and other embodiments associated with clock generation are provided. In one embodiment, an apparatus comprises a digital clock circuit. Receive logic is configured to receive a...
8595523 Data writing method for non-volatile memory, and controller and storage system using the same  
A data writing method for writing data from a host system into a plurality of memory dies of a rewritable non-volatile memory storage apparatus is provided. The data writing method includes...
8588341 Data transfer circuit and data transfer method for clock domain crossing  
A circuit that transfers data between a first clock domain using a first clock and a second clock domain using a second clock synchronized with the first clock. The circuit comprises a data...
8589716 Clock integrated circuit  
The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more...
8589717 Serial peripheral interface  
For an integrated circuit (IC) that retrieves data from a memory device external to the IC, a novel memory interface module that generates a sampling clock to the memory device and samples the...
8588355 Timing recovery controller and operation method thereof  
A timing recovery controller capable of performing timing recovery for a data sequence at twice a symbol rate includes a sampler, a timing base device, a timing error detector and a timing lock...
8589718 Performance scaling device, processor having the same, and performance scaling method thereof  
A performance scaling device, a processor having the same, and a performance scaling method thereof are provided. The performance scaling device includes an adaptive voltage scaling unit, a...
8578404 Program telecast monitoring using watermarks  
Methods, apparatus and articles of manufacture for program telecast monitoring using watermarks are disclosed. An example method for program monitoring disclosed herein comprises obtaining a...
8572425 Data processing device and mobile device  
A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface...
8566632 Multi-rate sampling for network receiving nodes using distributed clock synchronization  
Various embodiments relate to a network receiver using distributed clock synchronization. The network receiver may include a first timing engine that samples bits received by the receiver with a...
8560876 Clock acceleration of CPU core based on scanned result of task for parallel execution controlling key word  
In a computing system having a multi-core central processing unit (CPU) having at least two cores, it is determined that a task to be scheduled meets clock acceleration criteria such as requiring...
8555104 Frequency adapter utilized in high-speed internal buses  
A frequency adapter for synchronizing data transfers between a low-frequency module and a high-frequency module connected to an internal bus. The frequency adapter includes a low-to-high...
8549344 Method for reducing electromagnetic emissions in a multiple micro-controller device  
A method for reducing electromagnetic emissions in an electronic device having a multiple micro-controllers includes identifying the number of micro-controllers installed in the electronic device....
8549329 System power management using memory throttle signal  
According to some embodiments, power information associated with a computing system may be monitored. Based on the monitored power information, it may be determined whether a hardware memory...
8549343 Timing recovery apparatus and method thereof  
A multimedia processing system for processing a program stream containing a program clock reference information. The system comprises a clock generator, a timer, a modifier, a processing unit, a...
8548616 Digital audio device  
A digital audio device has a plurality of input ports that are provided with a plurality of digital audio signals. A plurality of extraction parts extract a clock signal from the digital audio...
8549342 Method and apparatus for fine edge control on integrated circuit outputs  
A device for adjusting the timing of at least one edge of an output pulse created in response to a reference pulse is disclosed. Such a device may include a first memory circuit having two or more...
8543860 Multi-core clocking system with interlocked ‘anti-freeze’ mechanism  
A clocking system, comprises a plurality of clocked data processing devices and a clock control circuit controlling a generation of a plurality of clock signals and an application of the clock...