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8473771 Integrated circuit having frequency dependent noise avoidance  
A clock source generates a first clock signal for clocking a first clocked module and a rate adapting module produces an operation dependent clock signal from the first clock signal for clocking a...
8468286 Variable-frequency bus adapter, adapting method and system  
A variable-frequency bus adapter, a variable-frequency bus adapting method and a variable-frequency bus adapting system are provided. The method includes: generating a bus blocking indication...
8464042 Performance adjustment apparatus and method of information processing apparatus  
A performance adjustment apparatus connected to an information processing apparatus includes a performance adjustment unit that controls operation processing performance of an operation processing...
8458507 Bus frequency adjustment circuitry for use in a dynamic random access memory device  
A clock divider circuitry and method for use in a dynamic random access memory device. The method may include receiving a clock input signal having a first frequency from a clock input receiver at...
8453006 Command decoding method and circuit of the same  
A decoding circuit for decoding a command is provided. The received command is transmitted during at least two clock periods of a clock signal, and the received command is divided to a former...
8452908 Low latency serial memory interface  
A device applies synchronous clocking across a first component and a second component of the device, and designates a particular serial link, from a group of serial links, as a master serial link....
8448008 High speed clock control  
On-chip high speed clock control techniques for testing circuits with multiple clock systems are disclosed. The techniques allow certain (e.g. compatible) high speed clocks to be activated with...
8448011 Increasing processor operating frequency when monitored loading level pattern of program matches recorded pattern of target program  
A data processing system and an adjusting method thereof are disclosed. The data processing system includes a processor, a clock generator, a monitoring module and a determining module. When a...
8448010 Increasing memory bandwidth in processor-based systems  
The amount of data that may be transferred between a processing unit and a memory may be increased by transferring information during both the high and low phases of a clock. As one example, in a...
8443224 Apparatus and method for decoupling asynchronous clock domains  
A circuit and method for synchronizing signals between asynchronous clock domains within digital electronic circuits decouples asynchronous clocks. The timing of the slower clock is used to prevent...
8443225 Method and apparatus synchronizing integrated circuit clocks  
Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin...
8433944 Clock divider system and method with incremental adjustment steps while controlling tolerance in clock duty cycle  
In a particular embodiment, a single step increment calculation module is responsive to a first ramp control value and a second ramp control value. The single step increment calculation module...
8429440 Flat panel display driver method and system  
Methods and systems are described for enabling display system data transmission during use. An integrated circuit package includes input interface circuitry configured to receive an audio-video...
8429442 Deriving accurate media position information  
Various embodiments utilize different counters or clocks, working in concert, to smooth out position information that is derived for a rendering/capturing device. Specifically, in at least some...
8429367 Systems, methods and apparatuses for clock enable (CKE) coordination  
Embodiments of the invention are generally directed to systems, methods, and apparatuses for clock enable (CKE) coordination. In some embodiments, a memory controller includes logic to predict...
8429441 Operating processor below maximum turbo mode frequency by sending higher than actual current amount signal to monitor  
A method, computer program product and system for controlling the maximum turbo mode of a processor in a turbo boost state. The method comprises limiting a maximum turbo mode available to the...
8423814 Programmable drive strength in memory signaling  
Embodiments of the invention relate to programmable data register circuits and programmable clock generation circuits For example, some embodiments include a buffer circuit for receiving input data...
8423659 Systems and methods for synchronizing operations among a plurality of independently clocked digital data processing devices that independently source digital data  
In a system for distributing data, distribution device is configured to distribute timestamp, offset and source location information for a digital data stream to an execution device, and the...
8417985 Adjusting system clock to faster speed upon receiving mass storage command and back to lower speed upon completion of all commands  
In a first embodiment of the present invention, a method for dynamically adjusting a system clock of a plurality of system clock-controlled components in a system is provided, the method...
8417986 Time negotiation using serial voltage identification communication  
According to some embodiments, a method and system are provided to initiate communication at an integrated circuit that is electrically coupled to a plurality of voltage regulators, determine a...
8417983 Adjusting a device clock source to reduce wireless communication interference  
Adjusting a clock source of a device clock to reduce wireless communication (e.g., radio frequency (RF)) interference within a device. The device clock may be derived from an input clock to a...
8412974 Global synchronization of parallel processors using clock pulse width modulation  
A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter....
8412976 Data negotiation using serial voltage identification communication  
According to some embodiments, a method and system are provided to initiate communication at an integrated circuit that is electrically coupled to a plurality of voltage regulators, determine a...
8412970 Optimizing power usage by factoring processor architectural events to PMU  
A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot....
8412975 USB based synchronization and timing system  
A synchronization apparatus, comprising: a USB device having a USB microcontroller, circuitry for observing USB traffic, and circuitry for decoding from a USB data stream a periodic data structure...
8407508 Serial bus clock frequency calibration system and method thereof  
A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device, a second frequency calibration device and a...
8402303 Method for encoder frequency shift compensation  
The embodiments disclose a method for encoder frequency-shift compensation, including, determining frequency values of an input encoder signal, analyzing an encoder index clock signal and the input...
8402301 Delaying one-shot signal objects  
A device may include a processor to execute a thread. The processor may be further configured to execute a set of wrappers that are called from within the thread to invoke a set of one-shot signal...
8397099 Using pulses to control work ingress  
The present invention extends to methods, systems, and computer program products for using pulses to control work ingress. Generally, embodiments of the invention use a variable-speed clock for...
8397098 Method for countervailing clock skew and core logic circuit using the same  
A method for countervailing clock skew between a first clock signal and a second clock signal in a core logic circuit. The second clock signal is sampled based on the first clock signal in a...
8397097 Computer system and operating method thereof  
A computer system is provided with an event counter, a CPU, a memory, an external device, a hub M31 and a hub I33. The computer system is further provided with a clock change module 50. System...
8397096 Heterogeneous physical media attachment circuitry for integrated circuit devices  
An integrated circuit includes physical media attachment (“PMA”) circuitry that includes two different kinds of transceiver channels for serial data signals. One kind of transceiver channel is ada...
8392739 Multi-core processor, its frequency conversion device and a method of data communication between the cores  
A multi-core processor and a frequency conversion device thereof as well as a method of communication between the cores are disclosed. Each processor core of the multi-core processor includes a...
8386681 Multiple communication channels on MMC or SD CMD line  
The claimed subject matter can provide an architecture that interfaces a single slave device such as a UICC smartcard with multiple host controllers. For example, a secondary host can be interfaced...
8386765 Method for the encrypted transmission of synchronization messages  
There is described a method for transmitting synchronization messages, for example PTP messages of the IEEE 1588 standard, the PTP message being inserted into a data packet in line with the...
8380897 Host computer, computer terminal, and card access method  
According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received...
8381012 Apparatus and method for redundant and spread spectrum clocking  
An apparatus and method for fault-tolerant and spread spectrum clocking. In one embodiment a master clock synthesizer circuit generates an output clock signal of varying frequency within a...
8375238 Memory system  
A memory controller takes in the first to (N−1)th pieces of data respectively in synchronization with the second to Nth return read clocks. The memory controller takes in the Nth piece of data f...
8375242 Clock and data recovery (CDR) method and apparatus  
Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method...
8375239 Clock control signal generation circuit, clock selector, and data processing device  
Provided are a technique for high-speed switching between clock signals different in frequency, and a clock-control-signal-generation circuit which serves to generate a control signal for clock...
8356203 Asynchronous interface circuit and data transfer method  
An asynchronous interface circuit for transferring a data stream between different clock domains, the asynchronous interface circuits includes a data holding circuit for sequentially receiving and...
8356202 System and method for reducing power consumption in a device using register files  
A device and method for reducing the power consumption of an electronic device using register file with bypass mechanism. The width of a pulse controlling the word write operation may be extended...
8352774 Inter-clock domain data transfer FIFO circuit  
The inter-clock domain data transfer FIFO circuit provides a circuit that transfers data between two clock domains of unrelated frequencies. The gate count is kept relatively low, thereby allowing...
8352696 Integrated circuit with bi-modal data strobe  
A memory device that has two operating modes. In the first mode the data strobe is source synchronous and is driven by the memory device when data is being transmitted. In the second mode the data...
8352794 Control of clock gating  
Clock signal control circuitry is disclosed along with a method for switching a clock between modes and a computer program product. The clock signal control circuitry is for receiving a clock...
8347133 Method for adjusting computer system and memory  
The invention provides an adjusting method of a system for changing a working frequency in an operation system for a computer system. The adjusting method includes establishing a look-up table, and...
8345507 Storage device, substrate, liquid container, system and control method of storage device  
A storage device includes a nonvolatile storage section; and a control section that controls the nonvolatile storage section, wherein the control section includes an access control section that...
8347000 System and method detecting cable plug status in display device  
A timing controller provides a cable plug status detection function by receiving a reference lock signal from a graphics system connected via a constituent cable and comparing the reference lock...
8347132 System and method for reducing processor power consumption  
A system and method for reducing active power in processors is disclosed. A method embodiment comprises the steps of determining when a particular logic block is inactive, determining the powered...
8341453 Transmission apparatus that transmits data according to a protocol, and method for measuring time in the transmission apparatus  
A transmission apparatus that transmits data according to a protocol has a timer, a memory, a processor, and a transmission unit. The processor stores, in the memory, type data indicating a single...