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8656205 Generating reference clocks in USB device by selecting control signal to oscillator form plural calibration units  
A USB device with a clock calibration function and a method for calibrating reference clocks of a USB device are provided. A USB 2.0 initial calibration is performed on the USB device in order to...
8656204 Security device meant to be connected to a processing unit for audio/video signal and method using such a device  
Example embodiments relate to a security device having two communication interfaces sharing at least one pin, each interface being capable of operating according to either of two predetermined...
8650424 Method and apparatus to control power consumption of a plurality of processor cores  
For one disclosed embodiment, a plurality of processor cores of a multicore processor may be operated at variable performance levels. One processor core may operate at a performance level different...
8635487 Memory interface having extended strobe burst for write timing calibration  
Methods and systems for calibrating parameters for communication between a controller and a memory device. A memory controller may be configured to calibrate one or more of the write latency and/or...
8631266 Semiconductor memory device and method of controlling the same  
A method of tuning a phase of a clock signal includes performing data training on a plurality of data pins through which data are input and output, in synchronization with a data clock signal;...
8626966 Embedded clock recovery  
Systems and methods and computer program products are disclosed to determine the source data rate even in cases where the sink device is not directly coupled to the source device. A method...
8621109 Adaptable management in sync engines  
Synchronization of two or more items can be optimized through the use of parallel execution of synchronization tasks and adaptable processing that monitors and adjusts for system loading. Two or...
8621253 Processor boost based on user interface demand  
A method and system for boosting a clock frequency for a processor in a mobile device based on user interface (UI) demand are described. In response to a user interaction through a UI in the mobile...
8612795 Segmented clock network for transceiver array  
One embodiment relates to a clocking network interconnecting an array of transceivers. The clocking network includes first and second series of multiplexers, each multiplexer in the first and...
8612786 Deep idle mode  
A deep idle mode for electronic devices is described, which provides significant power savings while allowing significantly shorter resumption times than experienced with a suspend mode. During...
8599642 Port enable signal generation for gating a memory array device output  
A method of generating a dynamic port enable signal for gating memory array data to an output node includes generating a programmable leading edge clock signal derivation of an input dynamic clock...
8601297 Systems and methods for energy proportional multiprocessor networks  
Energy proportional solutions are provided for computer networks such as datacenters. Congestion sensing heuristics are used to adaptively route traffic across links. Traffic intensity is sensed...
8595537 DLL phase detection using advanced phase equalization  
A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is...
8595527 Method of managing power of multi-core processor, recording medium storing program for performing the same, and multi-core processor system  
Provided are a method of managing power of a multi-core processor, a recording medium storing a program for performing the method, and a multi-core processor system. The method of managing power of...
8594575 Shifted channel characteristics for mitigating co-channel interference  
Methods and apparatuses for minimizing co-channel interference in communications systems are disclosed. A method in accordance with the present invention comprises shifting a characteristic of the...
8595540 Rendering a content stream based on a digital clock generated based on timing information  
Systems, methods, and other embodiments associated with clock generation are provided. In one embodiment, an apparatus comprises a digital clock circuit. Receive logic is configured to receive a...
8595523 Data writing method for non-volatile memory, and controller and storage system using the same  
A data writing method for writing data from a host system into a plurality of memory dies of a rewritable non-volatile memory storage apparatus is provided. The data writing method includes...
8588341 Data transfer circuit and data transfer method for clock domain crossing  
A circuit that transfers data between a first clock domain using a first clock and a second clock domain using a second clock synchronized with the first clock. The circuit comprises a data holding...
8589716 Clock integrated circuit  
The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more...
8589717 Serial peripheral interface  
For an integrated circuit (IC) that retrieves data from a memory device external to the IC, a novel memory interface module that generates a sampling clock to the memory device and samples the...
8588355 Timing recovery controller and operation method thereof  
A timing recovery controller capable of performing timing recovery for a data sequence at twice a symbol rate includes a sampler, a timing base device, a timing error detector and a timing lock...
8589718 Performance scaling device, processor having the same, and performance scaling method thereof  
A performance scaling device, a processor having the same, and a performance scaling method thereof are provided. The performance scaling device includes an adaptive voltage scaling unit, a latency...
8578404 Program telecast monitoring using watermarks  
Methods, apparatus and articles of manufacture for program telecast monitoring using watermarks are disclosed. An example method for program monitoring disclosed herein comprises obtaining a...
8572425 Data processing device and mobile device  
A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface...
8566632 Multi-rate sampling for network receiving nodes using distributed clock synchronization  
Various embodiments relate to a network receiver using distributed clock synchronization. The network receiver may include a first timing engine that samples bits received by the receiver with a...
8560876 Clock acceleration of CPU core based on scanned result of task for parallel execution controlling key word  
In a computing system having a multi-core central processing unit (CPU) having at least two cores, it is determined that a task to be scheduled meets clock acceleration criteria such as requiring a...
8555104 Frequency adapter utilized in high-speed internal buses  
A frequency adapter for synchronizing data transfers between a low-frequency module and a high-frequency module connected to an internal bus. The frequency adapter includes a low-to-high...
8549344 Method for reducing electromagnetic emissions in a multiple micro-controller device  
A method for reducing electromagnetic emissions in an electronic device having a multiple micro-controllers includes identifying the number of micro-controllers installed in the electronic device....
8549329 System power management using memory throttle signal  
According to some embodiments, power information associated with a computing system may be monitored. Based on the monitored power information, it may be determined whether a hardware memory...
8549343 Timing recovery apparatus and method thereof  
A multimedia processing system for processing a program stream containing a program clock reference information. The system comprises a clock generator, a timer, a modifier, a processing unit, a...
8548616 Digital audio device  
A digital audio device has a plurality of input ports that are provided with a plurality of digital audio signals. A plurality of extraction parts extract a clock signal from the digital audio...
8549342 Method and apparatus for fine edge control on integrated circuit outputs  
A device for adjusting the timing of at least one edge of an output pulse created in response to a reference pulse is disclosed. Such a device may include a first memory circuit having two or more...
8543860 Multi-core clocking system with interlocked ‘anti-freeze’ mechanism  
A clocking system, comprises a plurality of clocked data processing devices and a clock control circuit controlling a generation of a plurality of clock signals and an application of the clock...
8539275 Single wire serial interface  
A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock...
8533519 Motherboard with overclocking function for a plurality of components therein such that the overclocking function for the plurality of the components are enabled via an external input device  
A motherboard with overclocking and overvolting functions is provided. The motherboard with an overvolting function includes a specified component, a voltage regulator and a micro-controller. The...
8531893 Semiconductor device and data processor  
In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in...
8533522 Double data rate output circuit  
A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second...
8527804 Architecture and method for eliminating store buffers in a DSP/processor with multiple memory accesses  
A method and apparatus for controlling system access to a memory that includes receiving first and second instructions, and evaluating whether both instructions can architecturally complete. When...
8526601 Method of improving operational speed of encryption engine  
In the present method of implementing functioning of an encryption engine, a plurality of logic blocks are provided, each for running a function. Each function is run based on three variables, each...
8522067 Variable latency interface for read/write channels  
A variable latency interface and method for managing variable latency. An apparatus includes a storage device controller and a read/write channel coupled to the storage device controller by a...
8514654 Storage apparatus, substrate, liquid container, system, and control method of the storage apparatus  
A storage apparatus including a nonvolatile storage section and a control section controlling the nonvolatile storage section, wherein the control section has a detection circuit detecting floating...
8516292 Method and apparatus for providing symmetrical output data for a double data rate DRAM  
An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a...
8516293 System and method for implementing a cloud computer  
One embodiment is a clocking system for a computing environment. The system comprises a first set of processes executing in a first computing environment; a first local clock mechanism associated...
8510580 Power management for a system on a chip (SoC)  
In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to...
8503239 Device for controlling lock state of block in a semiconductor memory and method for controlling the same  
A block control device for a semiconductor memory and a method for controlling the same are disclosed, which relate to a technology for controlling a block operation state of a Low Power...
8504862 Device and method for preventing lost synchronization  
A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a...
8504868 Computer system with synchronization/desynchronization controller  
A computer system includes a processor, a submodule connected to the processor, an external access monitor configured to monitor a data transfer between the processor and the submodule, and a...
8504864 Data sensor coordination using time synchronization in a multi-bus controller area network system  
A method is provided for synchronizing time in an unsynchronized vehicle controller area network system. A master control unit receives a global time from a time synchronization source. The master...
8499186 Clock generator and USB module  
A clock generator is provided. The clock generator includes a crystal oscillator, an inverter coupled to the crystal oscillator in parallel, a first circuit and a second circuit. The crystal...
8499180 IC card with low precision clock  
An IC Card may include electronic components to receive a power supply and a main clock signal by a reader device. The power supply may be provided to a subset of the electronic components during a...