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8589718 Performance scaling device, processor having the same, and performance scaling method thereof  
A performance scaling device, a processor having the same, and a performance scaling method thereof are provided. The performance scaling device includes an adaptive voltage scaling unit, a latency...
8578404 Program telecast monitoring using watermarks  
Methods, apparatus and articles of manufacture for program telecast monitoring using watermarks are disclosed. An example method for program monitoring disclosed herein comprises obtaining a...
8572425 Data processing device and mobile device  
A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface...
8566632 Multi-rate sampling for network receiving nodes using distributed clock synchronization  
Various embodiments relate to a network receiver using distributed clock synchronization. The network receiver may include a first timing engine that samples bits received by the receiver with a...
8560876 Clock acceleration of CPU core based on scanned result of task for parallel execution controlling key word  
In a computing system having a multi-core central processing unit (CPU) having at least two cores, it is determined that a task to be scheduled meets clock acceleration criteria such as requiring a...
8555104 Frequency adapter utilized in high-speed internal buses  
A frequency adapter for synchronizing data transfers between a low-frequency module and a high-frequency module connected to an internal bus. The frequency adapter includes a low-to-high...
8549344 Method for reducing electromagnetic emissions in a multiple micro-controller device  
A method for reducing electromagnetic emissions in an electronic device having a multiple micro-controllers includes identifying the number of micro-controllers installed in the electronic device....
8549329 System power management using memory throttle signal  
According to some embodiments, power information associated with a computing system may be monitored. Based on the monitored power information, it may be determined whether a hardware memory...
8549343 Timing recovery apparatus and method thereof  
A multimedia processing system for processing a program stream containing a program clock reference information. The system comprises a clock generator, a timer, a modifier, a processing unit, a...
8548616 Digital audio device  
A digital audio device has a plurality of input ports that are provided with a plurality of digital audio signals. A plurality of extraction parts extract a clock signal from the digital audio...
8549342 Method and apparatus for fine edge control on integrated circuit outputs  
A device for adjusting the timing of at least one edge of an output pulse created in response to a reference pulse is disclosed. Such a device may include a first memory circuit having two or more...
8543860 Multi-core clocking system with interlocked ‘anti-freeze’ mechanism  
A clocking system, comprises a plurality of clocked data processing devices and a clock control circuit controlling a generation of a plurality of clock signals and an application of the clock...
8539275 Single wire serial interface  
A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock...
8533519 Motherboard with overclocking function for a plurality of components therein such that the overclocking function for the plurality of the components are enabled via an external input device  
A motherboard with overclocking and overvolting functions is provided. The motherboard with an overvolting function includes a specified component, a voltage regulator and a micro-controller. The...
8531893 Semiconductor device and data processor  
In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in...
8533522 Double data rate output circuit  
A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second...
8527804 Architecture and method for eliminating store buffers in a DSP/processor with multiple memory accesses  
A method and apparatus for controlling system access to a memory that includes receiving first and second instructions, and evaluating whether both instructions can architecturally complete. When...
8526601 Method of improving operational speed of encryption engine  
In the present method of implementing functioning of an encryption engine, a plurality of logic blocks are provided, each for running a function. Each function is run based on three variables, each...
8522067 Variable latency interface for read/write channels  
A variable latency interface and method for managing variable latency. An apparatus includes a storage device controller and a read/write channel coupled to the storage device controller by a...
8514654 Storage apparatus, substrate, liquid container, system, and control method of the storage apparatus  
A storage apparatus including a nonvolatile storage section and a control section controlling the nonvolatile storage section, wherein the control section has a detection circuit detecting floating...
8516292 Method and apparatus for providing symmetrical output data for a double data rate DRAM  
An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a...
8516293 System and method for implementing a cloud computer  
One embodiment is a clocking system for a computing environment. The system comprises a first set of processes executing in a first computing environment; a first local clock mechanism associated...
8510580 Power management for a system on a chip (SoC)  
In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to...
8503239 Device for controlling lock state of block in a semiconductor memory and method for controlling the same  
A block control device for a semiconductor memory and a method for controlling the same are disclosed, which relate to a technology for controlling a block operation state of a Low Power...
8504862 Device and method for preventing lost synchronization  
A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a...
8504868 Computer system with synchronization/desynchronization controller  
A computer system includes a processor, a submodule connected to the processor, an external access monitor configured to monitor a data transfer between the processor and the submodule, and a...
8504864 Data sensor coordination using time synchronization in a multi-bus controller area network system  
A method is provided for synchronizing time in an unsynchronized vehicle controller area network system. A master control unit receives a global time from a time synchronization source. The master...
8499186 Clock generator and USB module  
A clock generator is provided. The clock generator includes a crystal oscillator, an inverter coupled to the crystal oscillator in parallel, a first circuit and a second circuit. The crystal...
8499180 IC card with low precision clock  
An IC Card may include electronic components to receive a power supply and a main clock signal by a reader device. The power supply may be provided to a subset of the electronic components during a...
8499188 Processing device for determining whether to output a first data using a first clock signal or a second data using delay from the first clock signal according to a control signal  
An embodiment of a processing device includes a function unit and a control unit. The function unit receives input data and performs a specific operation to the input data to generate result data....
8495397 Computer system capable of adjusting operating frequency dynamically  
The present invention relates to a computer system capable of adjusting the operating frequency dynamically and comprises at least a processor voltage-adjusting unit, a clock-generating circuit, at...
8484501 System for delay locked loop control that provides delay interval stabilization  
The delay locked loop (“DLL”) delay interval can be locked to stop the DLL from wasting power in unnecessarily switching to synchronize the device with the DLL is associated to the system clo...
8484389 AV renderer peripheral with dual inerrupt lines for staggered interrupts  
An audio-video (AV) playback chain and rendering peripheral device 300 for generating two or more interrupts 306, 308 with a programmable delay 304 between them. Such are configured to prevent two...
8479030 Power management of components having clock processing circuits  
A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to...
8477896 Structure for window comparator circuit for clock data recovery from bipolar RZ data  
A clock-data recovery doubler circuit for digitally encoded communications signals is provided. A window comparator includes two thresholds. A clock output is created by the window comparator and...
8473766 Optimizing power usage by processor cores based on architectural events  
A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot....
8473771 Integrated circuit having frequency dependent noise avoidance  
A clock source generates a first clock signal for clocking a first clocked module and a rate adapting module produces an operation dependent clock signal from the first clock signal for clocking a...
8468286 Variable-frequency bus adapter, adapting method and system  
A variable-frequency bus adapter, a variable-frequency bus adapting method and a variable-frequency bus adapting system are provided. The method includes: generating a bus blocking indication...
8464042 Performance adjustment apparatus and method of information processing apparatus  
A performance adjustment apparatus connected to an information processing apparatus includes a performance adjustment unit that controls operation processing performance of an operation processing...
8458507 Bus frequency adjustment circuitry for use in a dynamic random access memory device  
A clock divider circuitry and method for use in a dynamic random access memory device. The method may include receiving a clock input signal having a first frequency from a clock input receiver at...
8453006 Command decoding method and circuit of the same  
A decoding circuit for decoding a command is provided. The received command is transmitted during at least two clock periods of a clock signal, and the received command is divided to a former...
8452908 Low latency serial memory interface  
A device applies synchronous clocking across a first component and a second component of the device, and designates a particular serial link, from a group of serial links, as a master serial link....
8448008 High speed clock control  
On-chip high speed clock control techniques for testing circuits with multiple clock systems are disclosed. The techniques allow certain (e.g. compatible) high speed clocks to be activated with...
8448011 Increasing processor operating frequency when monitored loading level pattern of program matches recorded pattern of target program  
A data processing system and an adjusting method thereof are disclosed. The data processing system includes a processor, a clock generator, a monitoring module and a determining module. When a...
8448010 Increasing memory bandwidth in processor-based systems  
The amount of data that may be transferred between a processing unit and a memory may be increased by transferring information during both the high and low phases of a clock. As one example, in a...
8443224 Apparatus and method for decoupling asynchronous clock domains  
A circuit and method for synchronizing signals between asynchronous clock domains within digital electronic circuits decouples asynchronous clocks. The timing of the slower clock is used to prevent...
8443225 Method and apparatus synchronizing integrated circuit clocks  
Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin...
8433944 Clock divider system and method with incremental adjustment steps while controlling tolerance in clock duty cycle  
In a particular embodiment, a single step increment calculation module is responsive to a first ramp control value and a second ramp control value. The single step increment calculation module...
8429440 Flat panel display driver method and system  
Methods and systems are described for enabling display system data transmission during use. An integrated circuit package includes input interface circuitry configured to receive an audio-video...
8429442 Deriving accurate media position information  
Various embodiments utilize different counters or clocks, working in concert, to smooth out position information that is derived for a rendering/capturing device. Specifically, in at least some...