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8386681 Multiple communication channels on MMC or SD CMD line  
The claimed subject matter can provide an architecture that interfaces a single slave device such as a UICC smartcard with multiple host controllers. For example, a secondary host can be interfaced...
8386765 Method for the encrypted transmission of synchronization messages  
There is described a method for transmitting synchronization messages, for example PTP messages of the IEEE 1588 standard, the PTP message being inserted into a data packet in line with the...
8380897 Host computer, computer terminal, and card access method  
According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received...
8381012 Apparatus and method for redundant and spread spectrum clocking  
An apparatus and method for fault-tolerant and spread spectrum clocking. In one embodiment a master clock synthesizer circuit generates an output clock signal of varying frequency within a...
8375238 Memory system  
A memory controller takes in the first to (N−1)th pieces of data respectively in synchronization with the second to Nth return read clocks. The memory controller takes in the Nth piece of data f...
8375242 Clock and data recovery (CDR) method and apparatus  
Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method...
8375239 Clock control signal generation circuit, clock selector, and data processing device  
Provided are a technique for high-speed switching between clock signals different in frequency, and a clock-control-signal-generation circuit which serves to generate a control signal for clock...
8356203 Asynchronous interface circuit and data transfer method  
An asynchronous interface circuit for transferring a data stream between different clock domains, the asynchronous interface circuits includes a data holding circuit for sequentially receiving and...
8356202 System and method for reducing power consumption in a device using register files  
A device and method for reducing the power consumption of an electronic device using register file with bypass mechanism. The width of a pulse controlling the word write operation may be extended...
8352774 Inter-clock domain data transfer FIFO circuit  
The inter-clock domain data transfer FIFO circuit provides a circuit that transfers data between two clock domains of unrelated frequencies. The gate count is kept relatively low, thereby allowing...
8352696 Integrated circuit with bi-modal data strobe  
A memory device that has two operating modes. In the first mode the data strobe is source synchronous and is driven by the memory device when data is being transmitted. In the second mode the data...
8352794 Control of clock gating  
Clock signal control circuitry is disclosed along with a method for switching a clock between modes and a computer program product. The clock signal control circuitry is for receiving a clock...
8347133 Method for adjusting computer system and memory  
The invention provides an adjusting method of a system for changing a working frequency in an operation system for a computer system. The adjusting method includes establishing a look-up table, and...
8345507 Storage device, substrate, liquid container, system and control method of storage device  
A storage device includes a nonvolatile storage section; and a control section that controls the nonvolatile storage section, wherein the control section includes an access control section that...
8347000 System and method detecting cable plug status in display device  
A timing controller provides a cable plug status detection function by receiving a reference lock signal from a graphics system connected via a constituent cable and comparing the reference lock...
8347132 System and method for reducing processor power consumption  
A system and method for reducing active power in processors is disclosed. A method embodiment comprises the steps of determining when a particular logic block is inactive, determining the powered...
8341453 Transmission apparatus that transmits data according to a protocol, and method for measuring time in the transmission apparatus  
A transmission apparatus that transmits data according to a protocol has a timer, a memory, a processor, and a transmission unit. The processor stores, in the memory, type data indicating a single...
8339869 Semiconductor device and data processor  
To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption. In a data processor having a bus controller that...
8341454 Rendering a video stream based on digital clock generated based on timing information  
Systems, methods, and other embodiments associated with clock generation are provided. In one embodiment, a precise timing protocol message is parsed to extract timing information. Timing waveform...
8335941 Method for reducing power consumption of a computer system in the working state  
A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with...
8332683 Data processing system and image processing system  
A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules...
8330746 Addressing method and structure for multiple chips and display system thereof  
Addressing method for multiple chips is provided. Each chip includes an input enable terminal, an output enable terminal, a data input terminal, and a clock terminal. The output enable terminal of...
8332682 Interface control device  
An interface control device includes a first interface, a second interface, a third interface, an interface controller and a clock supplying unit. The first interface is used to communicate with a...
8326364 High resolution, low power design for CPRI/OBSAI latency measurement  
As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, timing circuits are used to calculate the “round trip” latency across CPR...
8327180 Data processing device and mobile device  
A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface...
8321719 Efficient clocking scheme for a bidirectional data link  
A method for communication via a bidirectional data link between a processing device and a memory device. The memory device includes a clock source to generate a clock signal for driving a latching...
8321716 Integrated circuit having frequency dependent noise avoidance  
An integrated circuit includes first, second and third circuits, a clock module and a rate adapting module. The first circuit causes frequency dependent noise and is clocked based on a clock...
8321718 Clock control  
The present invention provides a processor comprising: an execution unit arranged to execute a plurality of program threads, clock generating means for generating first and second clock signals,...
8321713 Fast data access mode in a memory device  
A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the...
8316456 System and method for representing a secure time in a device based upon an insecure clock  
A system and method for providing modified rights information to an application on an electronic device. A centralized component monitors both a system clock and a secure clock. The centralized...
8307237 Precision oscillator for an asynchronous transmission system  
A precision oscillator for an asynchronous transmission system. An integrated system on a chip with serial asynchronous communication capabilities includes processing circuitry for performing...
8306652 Dual-band communication of management traffic in a blade server system  
In one embodiment, a communication system for a multi-blade server system includes a multi-drop serial bus network interconnecting a management module with each of a plurality of servers in a...
8301930 System and apparatus for transmitting phase information from a client to a host between read and write operations  
An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources...
8300752 Method, circuit, and design structure for capturing data across a pseudo-synchronous interface  
A structure for performing cross-chip communication with mesochronous clocks. The structure includes: a data delay line; a remote clock delay line; a structure that captures at least one value of a...
8296598 Double data rate output circuit and method  
A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second...
8291256 Clock stop and restart control to pipelined arithmetic processing units processing plurality of macroblock data in image frame per frame processing period  
A digital VLSI circuit is provided with functions in which the number of switching operations to supply electric power to each arithmetic operation unit is reduced in a restricted period of time...
8291257 Apparatus and method to compensate for injection locking  
A circuit and method has a processing unit, a master clock generator for providing a master clock and a plurality of phase-locked loops, each providing a respective clock signal. A plurality of...
8286014 Power management for a system on a chip (SoC)  
In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to...
8285897 Synchronized multichannel universal serial bus  
The invention provides a method and apparatus for providing a synchronized multichannel universal serial bus, the method in one aspect comprising supplementing the signal channels in the USB...
8286025 Selection of port adapters for clock crossing boundaries  
Methods and apparatus are provided for allowing efficient clock domain crossing management in programmable chip systems. Components associated with different clock domains can be analyzed. Clock...
8281176 Buffer circuit and method  
The disclosed embodiments relate to buffer circuits and methods. One embodiment is a buffer circuit that receives a data signal, a first clock signal and a second clock signal, the buffer circuit...
8276014 Stalling synchronisation circuits in response to a late data signal  
A data processing circuitry for processing data is disclosed. The data processing circuitry comprises: a plurality of synchronization circuits for capturing and transmitting the data in response to...
8271770 Computer motherboard with automatically adjusted hardware parameter value  
A computer motherboard with automatically adjusted hardware parameter values restarts automatically and proceeds with overclocking or power-saving operation in case the computer motherboard hangs...
8271827 Memory system with extended memory density capability  
A system including a central processing unit, a first memory channel being configured to couple the central processing unit to a first semiconductor memory unit, wherein the first memory channel is...
8271821 Flexible RAM clock enable  
A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic...
8271823 DLL phase detection using advanced phase equalization  
A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is...
8271824 Memory interface and operating method of memory interface  
A memory interface circuit includes a clock signal supply buffer configured to send a system clock signal which is supplied through a reference node, to a memory through a transmission line; a data...
8266470 Clock generating device, method thereof and computer system using the same  
A clock generating device, method thereof and a computer system using the same are provided. The clock generating device includes a PLL module and a tuning module. The PLL module receives a...
8266471 Memory device including a memory block having a fixed latency data output  
A memory block includes a memory circuit and a clock generation unit. The memory circuit may output read data in response to being clocked by a clock signal having a selectable delay that may be...
8266360 I2C-bus interface with parallel operational mode  
An electronic circuit has an interface for an I2C-bus. The interface comprises a first node for a clock line of the I2C-bus; a second node for a data line of the I2C-bus; and an I2C-bus controller...