Match Document Document Title
8867681 Transmission system, transmission device, and clock synchronization method  
A transmission system which couples a plurality of transmission devices to a control device includes a first transmission device which is one of the plurality of transmission devices; a first...
8862153 Automated portable call collection unit  
An automated portable call collection unit (APCCU) may gather information used in testing the accuracy of a wireless mobile device locating system. A GPS ground truth detector may detect the...
8856579 Memory interface having extended strobe burst for read timing calibration  
Methods and systems for calibrating parameters for communication between a controller and a memory device. A memory controller may be configured to calibrate one or more of the read latency and/or...
8856578 Integrated circuit device including skew adjustment circuit and skew adjustment method  
A skew adjustment circuit, provided in an integrated circuit device having a plurality of signal lines transmitting a plurality of signals respectively, and a plurality of buffer circuits to which...
8850248 Multi-core electronic system having a rate adjustment module for setting a minimum transmission rate that is capable for meeting the total bandwidth requirement to a shared data transmission interface  
A multi-core electronic system for accessing a data storage device includes a plurality of processors, a data transmission interface and a rate adjustment module. The processors respectively...
8850247 Power management for a system on a chip (SoC)  
In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to...
8850258 Calibration for source-synchronous high frequency bus synchronization schemes  
Embodiments provide bus synchronization system including a source module, a plurality of destination modules, and a data alignment controller. The source module is configured to synchronize a...
8850178 Method and apparatus for establishing safe processor operating points  
A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more...
8850257 Device and method for preventing lost synchronization  
A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a...
8850259 Systems and methods for precise generation of phase variation in digital signals  
Systems and methods are disclosed for precise generation of phase variation in digital signals. The disclosed signal generation embodiments generate a pattern of information bits that represents a...
8839018 Programmable mechanism for optimizing a synchronous data bus  
An apparatus including a JTAG interface, synchronous bus optimizer, core clocks generator, synchronous strobe driver, and a DLL. The JTAG interface receives control information indicating a first...
8832487 High-speed I/O data system  
In embodiments of a high-speed I/O data system, a first computer chip includes a data transmission system, and a second computer chip includes a data reception system. A data channel communicates...
8832488 Method and apparatus for digital I/O expander chip with multi-function timer cells  
A method and apparatus for digital I/O expander chip with multi-function timer cells have been disclosed. A series of match reload registers load a series of match registers which are driven by a...
8826063 Electronic device with reduced power consumption in external memory  
An electronic device for data processing is disclosed having a CPU (3), a Closely Coupled Memory (5), an external memory system (8), and a first clock unit (1) and second clock unit (9) for...
8826058 Delay tolerant asynchronous interface (DANI)  
A Delay-tolerant Asynchronous Interface (DANI) is typically used to make the clock domains for reusable silicon intellectual property (IP) cores completely independent of each other. In fact, a...
8819474 Active training of memory command timing  
Embodiments of the invention are generally directed to systems, methods, and apparatuses for the active training of memory command timing. In some embodiments, the CMD/CTL timing is actively...
8819473 Clock integrated circuit  
The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more...
8806066 Method for input output expansion in an embedded system utilizing controlled transitions of first and second signals  
A method for expanding input/output in an embedded system is described in which no additional strobes or enable lines are necessary from the host controller. By controlling the transitions of the...
8806257 Image processing apparatus and control method thereof  
Disclosed is an image processing apparatus, which can differently set a clock ratio according to a use rate of a CPU, and a control method thereof. The image processing apparatus may include a...
8806244 Systems and methods for energy proportional multiprocessor networks  
Energy proportional solutions are provided for computer networks such as datacenters. Congestion sensing heuristics are used to adaptively route traffic across links. Traffic intensity is sensed...
8806260 Method and apparatus for generating a clock signal and for controlling a clock frequency using the same  
A method and a device for generating a clock signal determine a number of pulses to be discarded from each predetermined cycle of a reference clock signal in order to obtain, on average, a target...
8806263 Methods and apparatuses including a global timing generator and local control circuits  
Apparatus and methods are disclosed, such as a global timing generator coupled to local control circuits. Each local control circuit can control programming and reading of a memory element in a...
8797868 Energy-efficient network device with coordinated scheduling and rate control using non-zero base power  
A network device of a communication network is configured to implement coordinated scheduling and processor rate control. In one aspect, packets are received in the network device and scheduled...
8799545 Restoring stability to an unstable bus  
A method for restoring stability to an unstable bus includes cycling a clock of the bus a number of times, transmitting a stop bit, cycling a clock line of the bus at least one time and...
8788870 Flat panel display driver method and system  
Methods and systems are described for enabling display system data transmission during use. An integrated circuit package includes input interface circuitry configured to receive an audio-video...
8788869 Interchangeable lens and camera body communicating whether data transmission was normal or abnormal  
An interchangeable lens that can be detachably fitted to a camera body includes: a clock signal reception unit that receives a clock signal outputted from the camera body; a control command...
8773927 Adjusting bit-line discharge time in memory arrays based on characterized word-line delay and gate delay  
A memory tracking circuit controls discharge duration of a tracking bit-line based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to...
8775857 Sequential on-chip clock controller with dynamic bypass for multi-clock domain testing  
A controller includes a clock control unit configured to provide a first output to test circuitry and a bypass unit configured to provide a second output to a further controller. The controller is...
8775853 Device and method for preventing lost synchronization  
A method for synchronizing two connection nodes by a reception node of the connection nodes with a clock data recovery circuit that generates a synchronization clock from input data. The method...
8773409 Skew adjusting apparatus, transmitting and receiving system, and skew adjusting method  
A skew adjusting apparatus includes: latching circuits that latch other signals in synchronism with transition timing of the signal level of a reference signal among signals transmitted with a...
8769177 Interrupt latency reduction  
A method in accordance with one embodiment of the invention can include detecting an interrupt request during execution of an instruction by a processor of an integrated circuit. Additionally, a...
8762763 Single-wire transmission interface and method of transmission through single-wire  
The present invention discloses a single-wire transmission interface, and a method of transmission through single-wire. The method comprises: providing a single-wire signal through a single-wire;...
8756452 Using pulses to control work ingress  
Pulses are used to control work ingress. Generally, a variable-speed clock is used for accepting work for lower-priority services. A clock rate is controlled by a load monitor. The load monitor...
8756446 Microprocessor having a low-power mode and a non-low power mode, data processing system and computer program product  
A microprocessor has a low-power mode and a non-low power mode. The microprocessor includes a processor core for executing instructions provided to the microprocessor and a clock providing a clock...
8756393 Control circuit in a memory chip  
Embodiments of the invention relate to a control circuit comprising a clock signal connection for receiving a system clock signal, a write signal connection for receiving a write signal, and a...
8751854 Processor core clock rate selection  
Techniques described herein generally relate to multi-core processors including two or more processor cores. Example embodiments may set forth devices, methods, and computer programs related to...
8751852 Programmable mechanism for delayed synchronous data reception  
An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, and a...
8751851 Programmable mechanism for synchronous strobe advance  
An apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, a core clocks generator, and a synchronous strobe driver. The JTAG interface is configured to receive...
8751850 Optimized synchronous data reception mechanism  
An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network, a composite delay element, and delay-locked loops (DLLs). The...
8745433 Memory device, board, liquid container, host device, and system  
A memory device includes a memory unit, a memory control unit that controls an access of the memory unit, a control unit that performs a communication process with a host device, a data terminal,...
8743633 Integrated semiconductor device  
An integrated semiconductor device including: a first semiconductor device having a clock generation section, first data storage sections storing input data as transfer data, data output terminals...
8738955 Semiconductor device and semiconductor system including the same  
A semiconductor device includes an internal circuit configured to perform a specified operation in response to a predetermined command; a normal data input/output section configured to...
8738769 Method, system, and storage medium for collecting SNMP bandwidth data  
A method, system, and storage medium for collecting bandwidth data is provided. The method includes producing master and slave text files in response to simultaneous collection of data samples...
8732513 Method and system for a message processor switch for performing incremental redundancy in edge compliant terminals  
Certain embodiments of the invention may be found in a method and system for processing messages. Aspects of the method may comprise receiving at least one signal on a chip that controls switching...
8732514 Using pulses to control work ingress  
Clock pulses of a variable speed clock are adjusted relative to system utilization. A load monitor periodically collects sensor measurements of resources and based on the sensor measurements, the...
8732495 Systems, apparatuses and methods for dynamic voltage and frequency control of components used in a computer system  
Embodiments of the present disclosure include systems, apparatuses, and methods for dynamic frequency and voltage control of components used in a computer system. A system includes a processor...
8724663 Implementation method and system, main control device and smart card for information transmission  
An implementation method and system, main control device and smart card for information transmission are provided. The method includes: the smart card notifying the main control device of the...
8726061 System and method for synchronizing multiple media devices  
Multiple media devices are synchronized in a multi-media system having a computer system, a plurality of media devices, and a display system. Each media device to be synchronized receives a...
8726062 Data recovery architecture (CDR) for low-voltage differential signaling (LVDS) video transceiver applications  
The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is...
8726057 Power management of components having clock processing circuits  
A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to...