Match Document Document Title
7392372 Method for memory initialization involves detecting primary quantity of memories and setting optimum parameters based on hardware information of memories  
A memory initialization method for a plurality of memories. The memories are initialized according to predetermined initial parameters. A first quantity of the memories is detected. Optimum...
7386638 System and method for pendant bus for serially chaining multiple portable pendant peripherals  
A communications system is arranged for serially chaining multiple portable pendant peripherals to a portable host device. The system enables multiple low power input/output peripherals to...
7386513 Networked services licensing system and method  
A method, system, and computer program product for exercising rights based on determining trust in an issuance of a rights expression, including issuing rights expressions by a chain of servers,...
7383460 Method and system for configuring a timer  
The present invention facilitates access to timers in a computing device. In particular, a timer system facilitates configuring a hardware interrupt timer in a computing device, the timer being...
7382366 Method, apparatus, system, and graphical user interface for selecting overclocking parameters of a graphics system  
Overclocking parameters in a graphics system are automatically set. In one embodiment, in response to a user request, overclocking parameters for different sets of overclocking parameters are...
7383458 Method and device for synchronizing the cycle time of a plurality of TTCAN buses based on determined global time deviations and corresponding bus system  
A method, a device, and a bus system for synchronizing at least two TTCAN buses having at least one bus user, there being cycle times of the basic cycles in the TTCAN buses, a global time being...
7383459 Apparatus and method for phase-buffering on a bit-by-bit basis using control queues  
One embodiment of the present invention provides a system that facilitates phase-buffering on a bit-by-bit basis using a control queue. The system includes a control queue, wherein a stage in the...
7380152 Daisy chained multi-device system and operating method  
A multi-device system having a daisy chain system bus structure and related method of operation are disclosed. A reference signal having a defined oscillation period is communicated around the...
7375560 Method and apparatus for timing domain crossing  
A timing domain crossing apparatus and method of transferring signals between timing domains are disclosed. A receiver samples a data signal with a sample clock in a first timing domain. The...
7376858 System comprising a plurality of slave devices coupled to a bidirectional ring bus and outputting a first and second clock signal from a first and second slave device respectively and selecting either the first or second clock signal at each slave device  
The objective is to reduce the downtime of a printing system in the printing industry. Provision is therefore made to supply the drive regulators (3) of a printing system (1) simultaneously with a...
7376856 Circuit arrangement  
An object of the present invention is to provide a circuit device in which the power consumption can be reduced without the dedicated signal. A circuit device (1) comprising a D flip-flop (F0) for...
7370168 Memory card conforming to a multiple operation standards  
The invention intends to provide a memory card conforming to an HS-MMC mode in a standard of a multimedia card, while securing compatibility of both standards of the multimedia card and an SD...
7370189 Method and apparatus for establishing safe processor operating points in connection with a secure boot  
A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more...
7366938 Reset in a system-on-chip circuit  
An electronic device having first circuitry operating in a first clock environment and second circuitry operating in a second clock environment, the first circuitry being arranged to generate a...
7366943 Low-latency synchronous-mode sync buffer circuitry having programmable margin  
Synchronization is attained between a source clock domain and a target clock domain of arbitrary frequency ratios and each of which periodically has edges nominally aligned to edges of a reference...
7366930 System and method for successfully negotiating a slowest common link speed between a first and second device  
According to some embodiments, an Ethernet link speed is determined based on a power-related configuration, and an Ethernet link is negotiated at the link speed. Embodiments may also include...
7366937 Fast synchronization of a number of digital clocks  
The present invention relates to a method for synchronizing a number of digital clocks to a synchronizing signal, said method comprising generating centrally a reference clock, synthesizing said...
7362834 Method and device for synchronizing at least one node of a bus system and a corresponding bus system  
Method of synchronizing at least one user of a bus system which is operated with a preselectable system clock period (NTU), a local clock period (LNTU) and a reference clock period (GNTU) being...
7360108 Multi-link receiver and method for processing multiple data streams  
A multi-link receiving mechanism (MRM) is disclosed comprising a plurality of receivers. Each receiver receives a separate data stream, and all receivers receive the same clock signal. The data...
7356726 Frequency control apparatus for controlling the operation frequency of an object  
A frequency control apparatus and an information processing apparatus includes an observation section for observing an operation state of a control object which operates with a variably controlled...
7356703 Time-based computer access controls  
The present disclosure provides systems and methods for controlling computer access. Briefly described in architecture, some embodiments of such a system provide an access control unit to regulate...
7353421 Method and apparatus for determining and allocating clock frequencies for plurality of processing units on system start-up or resetting of the system  
A method and apparatus for operating a computer system comprising a first and a second computing unit, the method comprising selecting a first clock frequency for operation of said first computing...
7350095 Digital circuit to measure and/or correct duty cycles  
A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However,...
7350093 Apparatus and method for generating a delayed clock signal  
An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock...
7350096 Circuit to reduce power supply fluctuations in high frequency/ high power circuits  
The present invention provides for a circuit for transitioning clocking speeds. A counter is coupled to the clocking means. A comparator is coupled to an output of the counter. A first divider is...
7350116 Clock synchronization and fault protection for a telecommunications device  
According to one embodiment, a telecommunications device includes a bus and a controller coupled to the bus that generates a system clock signal according to a first reference clock signal and...
7346794 Method and apparatus for providing clocking phase alignment in a transceiver system  
A method and apparatus for providing clock phase alignment in a transceiver system are disclosed. Circuits are provided for providing clock phase alignment to adjust and align the phase between...
7346710 Apparatus for input/output expansion without additional control line wherein first and second signals transition directly to a different state when necessary to perform input/output  
An apparatus for expanding I/O is described in which no additional strobes or enable lines are necessary from the host controller. By sequencing data in a specific way when output to two existing...
7346797 Optimum stable composite clock network  
An apparatus and method are disclosed or producing a network of composite clocks with optimized stability characteristics from individual clocks that are part of a network wherein not all clocks...
7343511 Method and apparatus for data transfer, image forming apparatus, and computer product  
In a data transfer apparatus a clock transmitting unit transmits a first clock to a target for data transfer that is situated at a distance from the data transfer apparatus, a data transmitting...
7343433 Method and apparatus for controlling amount of buffer data in a receiver of a data communication system, and method and apparatus for playing streaming data with adaptive clock synchronization unit  
A method and apparatus for controlling an amount of buffer data in a receiver of a data communication system, and a method and apparatus for playing back streaming data stored in a buffer, using...
7343512 Controlling clock rates of an integrated circuit including generating a clock rate control parameter from integrated circuit configuration  
Systems and methods for controlling clock rates of circuits are provided. The systems and methods, collectively referred to as clock rate control, generate a clock rate control parameter from data...
7343508 Dynamic clock control circuit for graphics engine clock and memory clock and method  
A variable clock control information generator receives graphics engine activity data relating to the operating level of a graphics engine, and memory activity data relating to an activity level...
7340633 Method for automatically detecting the clock frequency of a system clock pulse for the configuration of a peripheral device  
The present invention provides a method for automatic identification of the clock frequency of a system clock (15) for the configuration of a peripheral device (12), having the following steps:...
7340624 Clock control system and clock control method  
This invention relates to a clock control system including a CPU, a peripheral functional block for the CPU, a frequency multiplication circuit which multiplies the frequency of an input system...
7340634 Real time clock architecture and/or method for a system on a chip (SOC) application  
An apparatus comprising a first portion, a second portion and a processor. The first portion is configured to generate a count signal in response to a number of oscillations of a clock signal. The...
7340631 Drift-tolerant sync pulse circuit in a sync pulse generator  
A drift-tolerant sync generation circuit and sync generation method for a sync pulse generator operable in a clock synchronizer that effectuates data transfer between first circuitry disposed in a...
7337347 Information processing system and method for timing adjustment  
An elapsed cycle number during the predetermined period of the inputted clock source is counted using the clock reference signal as a yardstick, a frequency of the clock source is computed based...
7337259 Smart card virtual hub  
A smart card virtual hub combines an ISO7816 compliant smart card reader interface with a USB hub that provides one or more attachment points for connection of devices to the USB bus, thereby...
7337345 Input circuit for an electronic circuit and a method for controlling the reading-in of a data signal  
The invention relates to a method for controlling the reading-in of a data signal at an input of an electrical circuit to an input latch with the aid of a clock signal, with the data item, which...
7334148 Optimization of integrated circuit device I/O bus timing  
The invention includes a method to adjust integrated circuit device I/O bus timing. In one embodiment, the method includes comparing an alignment between an edge of a first clock signal to a...
7333962 Techniques to organize test results  
Techniques to organize test results are described. In one embodiment, for example, vectors with failure information may be generated from test result files. Nodes for a self-organizing map may be...
7334152 Clock switching circuit  
A clock switching circuit comprises: a composite clock generation circuit, which is to receive a first clock, a second clock, and a clock switching execution signal for switching between the first...
7334150 Memory module with a clock signal regeneration circuit and a register circuit for temporarily storing the incoming command and address signals  
A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command and address signals to the...
7330994 Clock control of a multiple clock domain data processor  
A processor clock control device operable to control a plurality of clock signals output to a processor, said processor comprising a plurality of domains each clocked by a respective one of said...
7328360 Maintaining synchronization of multiple data channels with a common clock signal  
Maintaining synchronization when sending/receiving multiple channels of data with a corresponding common reference clock signal. Synchronization signals (e.g., pulses) are generated periodically...
7327750 Receiving apparatus based on communications protocol  
An example receiving apparatus includes a reception clock controlling section for controlling clock supply to the components thereof. A reception section receives a communication packet...
7325152 Synchronous signal generator  
A synchronous signal generator is provided that contains a first and second counting and delay circuit, which both are in a subhierarchical position with respect to a reset signal...
7321979 Method and apparatus to change the operating frequency of system core logic to maximize system memory bandwidth  
A method, apparatus, and computer instructions for changing an operating frequency for a system core logic used to interface to memory in the multi-processor data processing system. A...
7321980 Software power control of circuit modules in a shared and distributed DMA system  
A system-on-chip integrated circuit selectively gates clocks to individual modules corresponding to the state of a corresponding bit of a peripheral enable register. A reset circuit supplies a...