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7472215 Portable computer system with thermal enhancements and multiple power modes of operation  
A portable computer adapted for electrical connection to a docking station having multiple power modes of operation is described. The portable computer has one or more CPU chips which have at...
7469356 Signals crossing multiple clock domains  
Methods, systems, and circuits are provided for signals crossing multiple clock domains. One circuit includes a number of different clock domains located on different portions of the ASIC. A...
7469355 Auto tune dynamic over clocking  
Methods, apparatuses, and systems are presented for dynamically overclocking a processor comprising operating the processor at a clock rate to run an executable program by using the processor to...
7469338 System and method for cryptographic control of system configurations  
Systems and methods are disclosed for using cryptographic techniques to configure data processing systems. A configuration manager cryptographically controls the configuration of a system by...
7469357 Method and apparatus for dynamic power management in an execution unit using pipeline wave flow control  
Power is conserved by dynamically applying clocks to execution units in a pipeline of a microprocessor. A clock to an execution unit is applied only when an instruction to the execution unit is...
7466723 Various methods and apparatuses for lane to lane deskewing  
Various methods, apparatuses and systems are described in which a skew delay time between communication lanes is determined. A data transfer path is established which includes two or more...
7467277 Memory controller operating in a system with a variable system clock  
The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a...
7464287 Strategy to verify asynchronous links across chips  
Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over...
7461287 Elastic interface de-skew mechanism  
A mechanism for de-skewing and aligning data bits sent between two chips on an elastic interface. On the receiving end of an elastic interface, the eye of each data bit within a clock/data group...
7460989 Method and apparatus for modeling multiple concurrently dispatched instruction streams in super scalar CPU with a sequential language  
A method is provided, wherein a virtual internal master clock is used in connection with a RISC CPU. The RISC CPU comprises a number of concurrently operating function units, wherein each unit...
7461286 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding  
A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an...
7457904 Methods and systems for a reference clock  
In at least some embodiments, a method comprises receiving an external card detection signal that indicates that a hot-pluggable card is coupled to a computer system and activating at least one...
7454646 Efficient clocking scheme for ultra high-speed systems  
There is provided a system for comparing the phase characteristics of three generated clock signals, each having a unique phase relationship with an original clock signal, with the original clock...
7454651 Main-board without restriction on memory frequency and control method thereof  
A main-board comprises a CPU, a chipset and a clock-rate control-signal generating module. The chipset has at least a phase-locked circuit, a CPU-bus circuit and a memory-bus circuit. The...
7454650 Microcontroller having a system resource prescaler thereon  
A microcontroller operating in synchronization with clock includes: an arithmetic unit operating in synchronization with the clock; an internal resource being connected to the arithmetic unit via...
7451337 Guaranteed edge synchronization for multiple clocks  
A method and apparatus for guaranteeing clock edge synchronization is disclosed. In one embodiment, a system for synchronizing clock signals includes a clock unit and a synchronization unit. Both...
7451338 Clock domain crossing  
Provided are a method, system, and device to effectuate a transfer of data from one clock domain to another. In accordance with one aspect of the description provided herein, bits of data to be...
7451334 Pipeline module circuit structure with reduced power consumption and method of operating the same  
A pipeline module circuit structure with reduced power consumption and a method for operating the pipeline module circuit structure are provided. The pipeline module circuit structure comprises a...
7451292 Methods for transmitting data across quantum interfaces and quantum gates using same  
Quantum gaps exist between an origin and a destination that heretofore have prevented reliably utilizing the advantages of quantum computing. To predict the outcome of instructions with precision,...
7447919 Voltage modulation for increased reliability in an integrated circuit  
Techniques are disclosed for increasing reliability of an integrated circuit. In one embodiment, an integrated circuit includes core chip circuitry. The integrated circuit includes means for...
7444535 Method and related apparatus for adjusting timing of memory signals  
A method and related apparatus for adjusting/calibrating timing of memory signals. In a preferred embodiment of the invention, reference signals of the same frequency and different phase are...
7441138 Systems and methods capable of controlling multiple data access using built-in-timing generators  
When receiving request commands from different hosts, a data system generates corresponding phase control signals and access signals based on the formats of each request command. Based on the...
7437592 Information processing device using variable operation frequency  
An information processing apparatus and an information processing method for use therewith are provided so as to implement optimal signal processing without deterioration of performance when using...
7434080 Apparatus for interfacing and testing a phase locked loop in a field programmable gate array  
An apparatus for interfacing a phase locked loop in a field programmable gate array. The apparatus comprising a phase locked loop cluster. The phase locked loop further comprising a plurality of...
7434083 Method and apparatus for the generation and control of clock signals  
Methods and apparatuses for the dynamic configuring of profiles used for the control of the frequency of clock signals. At least one embodiment of the present invention provides a means of...
7434084 Method and apparatus for eliminating sampling errors on a serial bus  
A synchronous bit-serial data interface utilizes a transmitter that transmits a data stream having duplicates of each data bit. The receiver samples the data stream utilizing either the rising or...
7434171 Performance control apparatus  
A variety of performance control mechanisms are disclosed, allowing a user of a processor-based system to adjust performance criteria such as processing speed and fan speed. A performance control...
7430681 Methods and apparatus for interfacing a drawing memory with a remote display controller  
A method of transmitting encoded computer display images between computers over a nondeterministic network is disclosed. During a display session in which images are transmitted from a host to a...
7428653 Method and system for execution and latching of data in alternate threads  
An alternate multi-thread pipeline structure and method are provided. A deep pipeline is provided in which two threads of two separate pipeline stages are alternatively presented to the various...
7428652 Programmable phase generator for cross-clock communication where the clock frequency ratio is a rational number  
A method and apparatus to support communication between components in different clock domains having a rational clock frequency ratio of N/D. In one embodiment, a combination of integer phase...
7426651 System and method for encoding independent clock using communication system reference clock  
A value representing a clock, such as a video clock, that is independent of the clock of a communication system, is encoded using the communication system clock and then sent with the video for...
7424636 Method and apparatus for controlling a clock signal of a line card circuit  
A method and apparatus for handling, maintaining, and controlling network synchronization information emanating from a plurality of line card circuits is described. The technique described may be...
7424635 System and method for power saving delay locked loop control by selectively locking delay interval  
The delay locked loop (“DLL”) delay interval can be locked to stop the DLL from wasting power in unnecessarily switching to synchronize the device with the DLL is associated to the system clock....
7421611 Scaling dynamic clock distribution for large service provider networks  
A system and method are disclosed for dividing a network into clock partitions to limit the overhead created by transmitting clock sources. A clock partition can be implemented through several...
7421606 DLL phase detection using advanced phase equalization  
A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is...
7421607 Method and apparatus for providing symmetrical output data for a double data rate DRAM  
An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a...
7421610 Clock generation circuit  
A clock generation circuit for an integrated circuit device, such as an SOC, has increased test coverage. The clock generation circuit includes first and second latches that receive an input clock...
7418601 Data transfer control system  
A data transfer control system includes a PC and a camera, and these are connected by a USB cable in a manner capable of making a communication with each other. Prior to a data transfer, the PC...
7418617 Apparatus for adjusting timing of memory signals  
An adjusting circuit for adjusting timings of memory signals of a computer system is provided. The adjusting circuit includes: a clock generator for generating a plurality of reference signals,...
7415625 Policy table rule based processor side bus signaling  
A system and method for selecting a computer hardware component of a computing system to throttle based on a selection policy is disclosed. A co-thermal control system may receive a first signal...
7412618 Combined alignment scrambler function for elastic interface  
An interface alignment pattern for de-skewing data bits received on an elastic interface is disclosed. The interface alignment pattern is “busy” in that it has a high number of logic state...
7409572 Low power memory controller with leaded double data rate DRAM package arranged on a two layer printed circuit board  
An integrated circuit is provided that includes an execution engine and a memory controller. The execution engine is clocked at a first rate and the memory controller is clocked at a second rate...
7409474 Method and system for rate adaptation  
A media access controller, which includes an output buffer and a clock controller, is provided. The output buffer includes a first and second clock input. The first clock is configured to control...
7409573 Micro-controller having USB control unit, MC unit and oscillating circuit commonly used by the USB control unit and the MC unit  
A micro-controller includes a USB control unit, an MC unit having an operation mode and a stop mode and an oscillating circuit, which is commonly used by the USB control unit and the MC unit. The...
7409568 Power supply voltage droop compensated clock modulation for microprocessors  
A voltage source droop compensated clock modulation for microprocessors is described. Specifically, the circuit reduces the clock frequency if a voltage source droop is detected.
7401246 Nibble de-skew method, apparatus, and system  
De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.
7401245 Count calibration for synchronous data transfer between clock domains  
Systems and methods for implementing count calibration for synchronous data transfer between clock domains are disclosed. An exemplary system may include a count calibration circuit for...
7398414 Clocking system including a clock controller that uses buffer feedback to vary a clock frequency  
A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; one or more clock controllers having...
7395450 Synchronous/asynchronous interface circuit and electronic device  
An exemplary embodiment provides a synchronous/asynchronous interface circuit and an electronic device for coupling an asynchronous circuit block onto a globally synchronous circuit system. A...
7394830 System for synchronizing circuitry in an access network  
A master Timestamp Synchronization Circuit (TSC) in a Cable Modem Termination System (CMTS) estimates a master timestamp value for an upcoming time reference. The master TSC sends the master...