Match Document Document Title
7571341 Method and system for fast frequency switch for a power throttle in an integrated device  
The ability to change from a first bus ratio to a second bus ratio without draining the transaction queues of a processor.
7568118 Deterministic operation of an input/output interface  
In one embodiment, the present invention includes a method for receiving data from a second device in a first device, forwarding the data from an input/output (I/O) clock domain to a system clock...
7565564 Switching circuit and method thereof for dynamically switching host clock signals  
A switching circuit located in a computer system is disclosed in the present invention. The switching circuit comprises a first phase-locked loop generating a first host clock signal, a second...
7561582 Data reception device  
A data reception device having a reception data buffer unit storing a plurality of packets contained in a data packet, a reception data amount measuring unit measuring the data amount stored in...
7558980 Systems and methods for the distribution of differential clock signals to a plurality of low impedance receivers  
Systems and methods to distribute clock signals using a common bus. In one embodiment, a clock signal distribution system includes: a bus; a transmitter coupled to the bus to drive a clock signal...
7558530 Device for generating a clock signal  
A device for generating an output clock signal intended to time a digital processing circuit, said generating device receiving a first clock signal, characterized in that it comprises an...
7555670 Clocking architecture using a bidirectional clock port  
Embodiments of the invention are generally directed to systems, methods, and apparatuses for a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional...
7555669 Timing vector program mechanism  
Timing vectors are used to pass execution of time-dependent operations from firmware/software to a hardware component (e.g., a state machine). These vectors may be stored as a vector table in a...
7555585 Optimized performance and power access to a shared resource in a multiclock frequency system on a chip application  
A request from a first processor for access to a shared resource in a computing system is received, and access is provided to the shared resource by the first processor at a first clock frequency....
7552353 Controlling circuit for automatically adjusting clock frequency of a central processing unit  
A controlling circuit for automatically adjusting clock frequency of a CPU is provided. The controlling circuit includes: a current sensing circuit for converting a current signal of the CPU to a...
7552252 Memory interface circuit and method  
An interface circuit and method are described, in which the interface circuit includes a plurality of bi-directional buffers and logic, responsive to a read request from a system component,...
7549075 System and method for adjusting execution frequency of a central processing unit  
A method for adjusting execution frequency of a central processing unit (CPU) in an electronic apparatus is provided. The method includes the steps of: (a) obtaining a state of a CPU workload in...
7546480 High speed bus with alignment, re-timing and buffer underflow/overflow detection enhancements  
In a networked system in which high speed busses interconnect sources and destinations of data, systems for and methods of data alignment, data re-timing, and circular buffer underflow/overflow...
7545896 Asynchronous multi-clock system  
A system for controlling the transfer of a signal sequence in a first clock domain to a plurality of other clock domains. The system comprising: detecting circuitry for detecting receipt of the...
7543094 Target readiness protocol for contiguous write  
A method of performing contiguous write transactions on a processor bus according to an embodiment of the present invention includes detecting, by a bus agent, a request for a write cycle,...
7543172 Strobe masking in a signaling system having multiple clock domains  
Systems and methods for masking strobe signals in strobe-based systems are provided below. These strobe-masking systems receive a strobe signal from a component operating under one clock domain...
7539793 Synchronized multichannel universal serial bus  
The invention provides a method and apparatus for providing a synchronized multichannel universal serial bus, the method in one aspect comprising supplementing the signal channels in the USB...
7539889 Media data synchronization in a wireless network  
A method of keeping global time in a wireless network, the method comprising the steps of: using a first 802.11 chip set to read a Time Synchronization Function (TSF) to provide an initial time...
7536570 Microcontroller unit (MCU) with suspend mode  
A microcontroller unit having a suspend mode of operation includes a processing circuit for receiving digital information and processing said received digital information. Timing circuitry...
7536580 System and method for generating timer output corresponding to timer request from plurality of processes  
The present invention relates to timer generation corresponding to a plurality of timer requests, etc. necessary for task processes of a CPU and achieves efficient timer generation. The present...
7533286 Regulating application of clock to control current rush (DI/DT)  
In general, in one aspect, the disclosure describes an apparatus for engineering di/dt. The apparatus includes a plurality of functional blocks to perform different functions. The apparatus also...
7529910 Series and parallel operation of reconfigurable circuits with selection and timing buffers assembly for processing and binding divided data portions in matched timing  
A reconfigurable processor equipped with reconfigurable circuits (RCs) comprises unit A for dividing data input to the processor, and outputting a part of pieces of divided data to a RC, unit B...
7529962 System for expanding a window of valid data  
In one general embodiment, a design structure is provided including a first delay line having at least one buffer, the first delay line being for shifting a clock, a second delay line having at...
7523339 Information processing apparatus and media storage apparatus using the same  
An information processing apparatus switches a clock to reduce power consumption of an information processing unit. In order to reduce an overhead time in switching, the information processing...
7523245 Compact ISA-bus interface  
An I/O interface, compatible with industry standards, for interfacing a host to a peripheral device. The interface includes a clock signal, a bus, an address latch enable signal, a peripheral...
7523327 System and method of coherent data transfer during processor idle states  
Systems and methods of managing power provide for placing a processor in a non-snoopable state, where the processor is associated with a system memory. One or more data transfers between a...
7519005 Single-wire communication bus for miniature low-power systems  
A single-wire serial communications bus has a master device and one or more slave devices. The slave devices are addressed according to a predetermined addressing scheme in an address space. The...
7519849 Technique for providing service processor access to control and status registers of a module  
A technique for providing service processor (SP) access to registers, e.g., control and status registers (CSRs), located within hardware modules of a computer system, ensures access to the CSRs...
7519848 Data transfer apparatus  
A data transfer apparatus includes at least one master and a plurality of slaves connected by a ring-connection bus, and a controller having a master port and slave ports connected to the...
7519850 Method and unit for buffer control  
A system unit including a processor unit and an input storage unit. The processor unit generates an input signal and a clock signal. The input storage unit receives the input signal and the clock...
7518408 Synchronizing modules in an integrated circuit  
A synchronization system to synchronize modules (TX, RX) in an integrated circuit, such as a VLSI integrated circuit, in which the modules receive respective first and second clock signals...
7516349 Synchronized memory channels with unidirectional links  
A memory agent may include a first memory channel interface and a second memory channel, both with unidirectional links, and logic to synchronize a signal processed by the first memory channel...
7512827 Dual module clock supply for CAN communication module  
A CAN communication module (10) comprising a protocol kernel (14) and a CAN logic block (12) is provided. The protocol kernel includes a CAN bus interface and the CAN logic block includes a module...
7512828 Processor with flexible clock configuration  
A network processor or other type of processor includes clock generation circuitry which generates one or more clock signals for each of a number of clock domains of the processor. The clock...
7509517 Clock transferring apparatus for synchronizing input data with internal clock and test apparatus having the same  
There is provided a clock transferring apparatus that outputs input data given in synchronization with a transmission clock in synchronization with an internal clock having a phase different from...
7509514 Method and device for the sampling of digital data in synchronous transmission, with maintenance of binary integrity  
The method is applicable to the reception of data in the case of a digital transmission in which the pieces of data are transmitted by a unit of equipment A to a unit of equipment B with an...
7500132 Method of asynchronously transmitting data between clock domains  
A method of asynchronously transmitting data from a first clock domain to a second clock domain by transmitting the data from the first domain to a first register; after a first period of time,...
7496781 Timing signal generating circuit with a master circuit and slave circuits  
A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for...
7493511 Network media access controller embedded in a programmable logic device—transmit-side client interface  
A transmit-side client interface for a media access controller embedded in an integrated circuit having programmable logic is described. A media access controller core includes a transmit engine....
7493508 Information processing device, method, and program  
This invention relates to an information processing apparatus as well as to an information processing method and a program for use therewith, the apparatus being arranged to prevent a drop in its...
7492793 Method for controlling asynchronous clock domains to perform synchronous operations  
A method for controlling asynchronous clock domains to perform synchronous operations is provided. With the method, when a synchronous operation is to be performed on a chip, the latches of the...
7493535 JTAG circuit transferring data between devices on TCK terminals  
The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK...
7490258 Data processing device and mobile device  
A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface...
7487378 Asymmetrical IO method and system  
An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources...
7487379 High performance integrated circuit with low skew clocking networks and improved low power operating mode having reduced recovery time  
An integrated circuit includes a phase-locked-loop with fast clock synchronization recovery. A phase frequency detector is configured to receive a system clock signal and a feedback clock signal...
7480608 Method and system for reducing storage requirements of simulation data via KEYWORD restrictions  
Disclosed herein is a method of managing data results of simulation processing of a hardware description language (HDL) model based upon keywords. In accordance with the method, a restriction list...
7478255 Clock distribution in multi-cell computing systems  
Embodiments of the invention relate to distribution of clocks to CPUs in processing cells of a multi-cell system. In an embodiment, each cell includes an interface, referred to as an agent. A...
7478260 System and method for setting a clock rate in a memory card  
A memory card that includes a buffer configured to receive transactions, a storage media, and a control circuit coupled to the buffer and the storage media is provided. The control circuit is...
7475273 Hybrid parallel/serial bus interface  
A hybrid serial/parallel bus interface has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block...
7472306 Processor timing apparatus, systems, and methods  
An apparatus and a system, as well as a method and article, may operate to independently adjust a plurality of processor clocks coupled to a corresponding plurality of networked processors...