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7752480 System and method for switching digital circuit clock net driver without losing clock pulses  
A system and method for switching digital circuit clock net driver without losing clock pulses is presented. A device uses glitchless clock selection logic, which includes an edge detector, to...
7752481 Information processing apparatus and resume control method  
According to one embodiment, there is provided an information processing apparatus, including a first clock portion to output a first signal when a measurement value coincides with first set time,...
7752477 Signal processor and method for processing a signal  
A signal processor includes a reference clock generator configured to generate a reference clock as a synchronization reference for a signal processing. A counter is configured to count the...
7750963 Timing signal generating circuit and photographing device having same circuit  
A circuit for generating a timing signal, the circuit having a memory and a pulse generator, the timing signal consisting of a number of pulses. The memory stores pulse count data, including an...
7752476 Fast transition from low-speed mode to high-speed mode in high-speed interfaces  
Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable,...
7747795 Method and system for rate adaptation  
A media access controller to adapt a rate of an output signal to a rate of an output medium is provided. The media access controller includes a register configured to output data to an external...
7743273 Serial communication system and method for transmitting and receiving data in synchronization with a clock signal  
In a serial communication system in which data is transmitted from a first unit to a second unit in synchronization with a clock signal, the mode of communication between the first and second...
7739533 Systems and methods for operational power management  
Various systems and methods for power management are disclosed herein. For example, a synchronous semiconductor circuit is disclosed that includes two or more clock sources and a power management...
7739539 Read-data stage circuitry for DDR-SDRAM memory controller  
A circuit for sampling data from a memory device comprises a circuit for providing a clock signal to the memory device, a data bus carrying data at twice the rate of the clock signal, a circuit...
7739439 Method of fabrication of a portable computer apparatus with thermal enhancements and multiple modes of operation  
A portable computer adapted for electrical connection to a docking station having multiple power modes of operation is described. The portable computer has one or more CPU chips which have at...
7739538 Double data rate chaining for synchronous DDR interfaces  
A system and method in which the receiving chip separately latches each half of the data received from the double data rate bus. Each half is launched as soon as it is available; one on the normal...
7739537 Multiple clock domain microprocessor  
A multiple clock domain (MCD) microarchitecture uses a globally-asynchronous, locally-synchronous (GALS) clocking style. In an MCD microprocessor each functional block operates with a separately...
7734944 Mechanism for windaging of a double rate driver  
A double data rate launch system and method in which the two-to-one multiplexer select signal delay is programmable and can be adjusted individually for each system. This allows the amount of...
7725757 Method and system for fast frequency switch for a power throttle in an integrated device  
In one embodiment, the present invention includes a counter to count core clocks, where the counter has a value to be incremented from zero to one less than a first bus ratio. Coupled to the...
7725754 Dual clock interface for an integrated circuit  
A dual clock interface for an integrated circuit is described. An integrated circuit includes interface circuitry. The interface circuitry has a hardwired logic block. The hardwired logic block...
7725759 System and method of managing clock speed in an electronic device  
A method of controlling a clock frequency is disclosed and includes monitoring a plurality of master devices that are coupled to a bus within a system. The method also includes receiving an input...
7725756 Method for generating programmable data rate from a single clock  
A method for generating a wide range of clock rates from a single clock. A delta is generated from a first clock signal and a second clock signal. An accumulative offset is generated from adding...
7721133 Systems and methods of synchronizing reference frequencies  
System and methods of synchronizing reference frequencies are disclosed. In an exemplary implementation, a method may comprise providing separate reference frequencies for each of a plurality of...
7721027 Physical layer device having a SERDES pass through mode  
A physical layer device (PLD), comprising: a first serializer-deserializer (SERDES) device having a first parallel port; a second SERDES device having a second parallel port; a third SERDES device...
7716513 Self-tuning time interpolator  
A scaling factor used in time interpolation calculations is tuned so as to compensate for clock sources that generate timer interrupts both slower and faster than expected. The scaling factor is...
7716516 Method for controlling operation of microprocessor which performs duty cycle correction process  
A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a...
7716509 Storage and access control method for storage  
Embodiments of the invention prevent a storage from being continuously used in a state in which the time of a built-in clock is different from the actual time because of replacement of a battery...
7716510 Timing synchronization circuit with loop counter  
An apparatus for synchronizing an output clock signal with an input clock signal includes a first timing synchronization circuit, control logic, and a counter. The first timing synchronization...
7711976 Data processing system and image processing system  
A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules...
7711884 Method of operation of a portable computer apparatus with thermal enhancements and multiple modes of operation  
A portable computer adapted for electrical connection to a docking station having multiple power modes of operation is described. The portable computer has one or more CPU chips which have at...
7710101 Method and system for measuring maximum operating frequency and corresponding duty cycle for an I/O cell  
A circuit for measuring maximum operating frequency and its corresponding duty cycle for an input I/O cell implementation under test (IUT) includes a condition checking module, a central control...
7711975 Universal serial bus adaptive signal rate  
In some embodiments it is determined if a speed of a Universal Serial Bus cable of greater than 480 Mb per second is supported at each end of the Universal Serial Bus cable, the length of the...
7707450 Time shared memory access  
Apparatus and method are provided for accessing information in a storage area including a storage area which is accessible by a first buss and a second buss. The access by the first buss is...
7707000 Test instrument and system responsive to execution time data  
Test instruments constituting an automatic test system are characterized in terms of execution time data. The execution time data is composed of a set of execution times. Each of the execution...
7702837 Method of fabricating a portable computer apparatus with thermal enhancements and multiple modes of operation  
A portable computer adapted for electrical connection to a docking station having multiple power modes of operation is described. The portable computer has one or more CPU chips which have at...
7702942 Method for generating adjustable MRAM timing signals  
A variable timing system for a magnetoresistive random access memory circuit (MRAM IC) is embedded in an MRAM IC and includes a number of timing control circuits, where each timing control circuit...
7702945 Semiconductor device and communication control method  
The present invention relates to a technique capable of establishing communications between cores, which can provide a large degree of freedom of clock frequencies settable in each core, and thus...
7697372 Access to printing material container  
The present invention provides a storage device that enables identification data to be readily rewritten and ensures normal completion of a data writing operation in a short time period. In the...
7698590 Method and apparatus for timing and event processing in wireless systems  
A digital baseband processor is provided for concurrent operation with different wireless systems. The digital baseband processor includes a digital signal processor for executing digital signal...
7694042 Instantaneous data-driven clock-gating device and hard-wired streaming processing system including the same  
Digital logic processing devices capable of reduced power consumption may be provided. A digital logic processing device may include one or more processing elements, an input FIFO for storing...
7694053 Slave assembly for determining source of data received over a two-wire master-slave communications bus  
A method of determining a source of data received over a two-wire master-slave communication bus includes monitoring with a slave assembly a plurality of clock signals each generated by a master...
7694057 Portable computer apparatus with thermal enhancements and multiple modes of operation  
A portable computer adapted for electrical connection to a docking station having multiple power modes of operation is described. The portable computer has one or more CPU chips which have at...
7688925 Bit-deskewing IO method and system  
An IO method and system for bit-deskewing are described. Embodiment includes a computer system with multiple components that transfer data among them. In one embodiment, a system component...
7689821 Processor with configurable association between interface signal lines and clock domains  
A network processor or other type of processor includes an interface comprising a plurality of signal lines, and interface circuitry adapted to receive clock signals for respective interface clock...
7689740 System and method for serial-peripheral-interface data transmission  
The invention provides a method for Serial-Peripheral-Interface (SPI) data transmission. First, data stored in a first buffer of an SPI controller is transmitted to a second buffer of an SPI...
7689846 Method and apparatus for increasing the operating frequency of an electronic circuit  
One embodiment of the present invention provides a system that facilitates temporarily increasing the operating frequency of an electronic circuit, such as a computer system, beyond a maximum...
7689856 Mesochronous clock system and method to minimize latency and buffer requirements for data transfer in a large multi-processor computing system  
A mesochronous clock system and method to minimize latency and buffer requirements for data transfer in a large multiprocessor computing system. A stream of data is transferred from a first clock...
7685455 Semiconductor integrated circuit which generates internal clock signal for fetching input data synchronously with the internal clock signal without decrease of timing margin  
A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different...
7681066 Quantifying core reliability in a multi-core system  
A system may comprise a first processor core, a second processor core and a processor core assignor. The first processor core may include a first circuit to generate a first data and a second...
7681065 Method and system for a message processor switch for performing incremental redundancy in edge compliant terminals  
Certain embodiments of the invention may be found in a method and system for processing messages. Aspects of the method may comprise receiving at least one signal on a chip that controls switching...
7681199 Time measurement using a context switch count, an offset, and a scale factor, received from the operating system  
Systems, methods, and devices are provided for time measurement. One embodiment includes a method for measuring time on multiprocessor systems. The method includes allocating a memory space to a...
7681067 Bus system  
It is so arranged that an appropriate deadline is assured with little consumption of power. A register (24) for remaining transfer time senses time that remains up to a limit by which data is to...
7676685 Method for improving the data transfer in semi synchronous clock domains integrated circuits at any possible m/n clock ratio  
A method for data transfer between two semi-synchronous clock domains in a System on Chip (SoC) includes first and second integrated processors or circuits respectively operating at first and...
7676684 Semiconductor device and signal processing method for synchronizing data with a data strobe signal  
In view of accurately determine a valid range of data to be synchronized to the system clock, conforming to actual environments of mounting and connection, the semiconductor device of the present...
7676686 Delay locked loop circuit and synchronous memory device including the same  
A delay locked loop (DLL) circuit for a synchronous dynamic random access memory (SDRAM) enables a more stable operation when the semiconductor operates in a power-down mode for low power. The...