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7404099 Phase-locked loop having dynamically adjustable up/down pulse widths  
According to embodiments of the present invention, a phase-locked loop (PLL) may include circuitry to select a wide pulse width for the phase-frequency detector control signal when the PLL is in a...
7401246 Nibble de-skew method, apparatus, and system  
De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.
7398413 Memory device signaling system and method with independent timing calibration for parallel signal paths  
A memory system includes a memory controller and a memory component coupled to each other. The memory controller includes an interface to receive a first signal and a second signal from the memory...
7398412 Measure controlled delay with duty cycle control  
The disclosed embodiments relate to circuits that produce synchronized output signals. More specifically, there is provided a synchronization circuit adapted to receive an input signal, the...
7398411 Self-calibrating time code generator  
Provided is a self-calibrating time code generator and method for generating an accurate time code (e.g., an accurate IRIG waveform). The self-calibrating time code generator includes a...
7394830 System for synchronizing circuitry in an access network  
A master Timestamp Synchronization Circuit (TSC) in a Cable Modem Termination System (CMTS) estimates a master timestamp value for an upcoming time reference. The master TSC sends the master...
7392419 System and method automatically selecting intermediate power supply voltages for intermediate level shifters  
The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a...
7383459 Apparatus and method for phase-buffering on a bit-by-bit basis using control queues  
One embodiment of the present invention provides a system that facilitates phase-buffering on a bit-by-bit basis using a control queue. The system includes a control queue, wherein a stage in the...
7380152 Daisy chained multi-device system and operating method  
A multi-device system having a daisy chain system bus structure and related method of operation are disclosed. A reference signal having a defined oscillation period is communicated around the...
7376857 Method of timing calibration using slower data rate pattern  
An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than...
7376856 Circuit arrangement  
An object of the present invention is to provide a circuit device in which the power consumption can be reduced without the dedicated signal. A circuit device ( 1 ) comprising a D flip-flop (F 0 )...
7373541 Alignment signal control apparatus and method for operating the same  
Broadly speaking, an apparatus and associated method of operation is provided for controlling alignment signal transmission in an electronic communication process. More specifically, a programmable...
7369623 Apparatuses to simultaneously distribute clock signals and data on integrated circuits, interposers, and circuit boards  
A technique is described for simultaneously and synchronously transmitting digital data and a clock signal in a digital integrated circuit, circuit board, or system. The technique is based on the...
7366941 Wavefront clock synchronization  
The invention provides for the arrangement and management of timing of various domains on a large integrated circuit which introduces a phase offset between clock domains of neighboring cells to...
7366940 Multiprotocol computer bus interface adapter and method  
A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time base generator receives a clock...
7366939 Providing precise timing control between multiple standardized test instrumentation chassis  
Precise timing control across multiple standardized chassis such as PXI is obtained by providing several control signals over PXI_LOCAL within each chassis, and by providing these control signals...
7366938 Reset in a system-on-chip circuit  
An electronic device having first circuitry operating in a first clock environment and second circuitry operating in a second clock environment, the first circuitry being arranged to generate a...
7366937 Fast synchronization of a number of digital clocks  
The present invention relates to a method for synchronizing a number of digital clocks to a synchronizing signal, said method comprising generating centrally a reference clock, synthesizing said...
7356725 Method and apparatus for adjusting a time of day clock without adjusting the stepping rate of an oscillator  
A system, method and computer program product for steering a time-of-day (TOD) clock for a computer system having a physical clock providing a time base for executing operations that is stepped to...
7356723 Method and apparatus for data transfer  
A memory system and method according to various aspects of the present invention comprises a memory and an adaptive timing system for controlling access to the memory. The adaptive timing system...
7353420 Circuit and method for generating programmable clock signals with minimum skew  
A programmable clock deskewer generates an output clock with minimal clock skew. This is accomplished by means of a single series path coupling the input clock to the output clock. The programmable...
7353419 Apparatus and method to balance set-up and hold times  
A circuit for data/clock deskewing includes a data delay circuit and a clock circuit. The data delay circuit is arranged to select a delay for the data signal responsive to a data delay signal. The...
7353418 Method and apparatus for updating serial devices  
The present invention provides a method and apparatus for updating serial devices. The apparatus includes a plurality of serial registers. The apparatus further includes a device adapted to provide...
7350096 Circuit to reduce power supply fluctuations in high frequency/ high power circuits  
The present invention provides for a circuit for transitioning clocking speeds. A counter is coupled to the clocking means. A comparator is coupled to an output of the counter. A first divider is...
7346798 Circuit and method for aligning transmitted data by adjusting transmission timing for plurality of lanes  
A circuit and a method for aligning transmitted data by adjusting transmission timing for a plurality of lanes. The method includes utilizing different initial values to reset a count value...
7346795 Delaying lanes in order to align all lanes crossing between two clock domains  
In some embodiments an apparatus and method may comprise a plurality of lanes between two clock domains, each lane comprising circuitry to generate a first signal when the lane may lose cycle...
7346794 Method and apparatus for providing clocking phase alignment in a transceiver system  
A method and apparatus for providing clock phase alignment in a transceiver system are disclosed. Circuits are provided for providing clock phase alignment to adjust and align the phase between...
7343510 Method and device for selecting one of multiple clock signals based on frequency differences of such clock signals  
A clock detection and selection circuit ( 100 ) can include a first counter ( 102 - 0 ) that generates a first count value CNT 1 according to a first clock signal CLK 1 and a second counter ( 102...
7340635 Register-based de-skew system and method for a source synchronous receiver  
A register-based de-skew system and method for a source synchronous receiver circuit domain. In one embodiment, a de-skew strobe generator operates responsive to at least one incoming strobe signal...
7340632 Domain crossing device  
A domain crossing device for use in a semiconductor memory device, including: a unit for comparing a phase of an internal clock signal with a phase of a delay locked loop (DLL) clock signal to...
7340631 Drift-tolerant sync pulse circuit in a sync pulse generator  
A drift-tolerant sync generation circuit and sync generation method for a sync pulse generator operable in a clock synchronizer that effectuates data transfer between first circuitry disposed in a...
7340630 Multiprocessor system with interactive synchronization of local clocks  
A multiprocessor computer system comprises multiple data processors, each with an internal clock for providing time stamps to application software. The processors take turns as synchronization...
7337347 Information processing system and method for timing adjustment  
An elapsed cycle number during the predetermined period of the inputted clock source is counted using the clock reference signal as a yardstick, a frequency of the clock source is computed based on...
7337345 Input circuit for an electronic circuit and a method for controlling the reading-in of a data signal  
The invention relates to a method for controlling the reading-in of a data signal at an input of an electrical circuit to an input latch with the aid of a clock signal, with the data item, which is...
7334152 Clock switching circuit  
A clock switching circuit comprises: a composite clock generation circuit, which is to receive a first clock, a second clock, and a clock switching execution signal for switching between the first...
7334148 Optimization of integrated circuit device I/O bus timing  
The invention includes a method to adjust integrated circuit device I/O bus timing. In one embodiment, the method includes comparing an alignment between an edge of a first clock signal to a center...
7331005 Semiconductor circuit device and a system for testing a semiconductor apparatus  
Methods and apparatus for testing a semiconductor device. A testing interface is configured to interface with an external test apparatus and a device under test (DUT). In one embodiment, the...
7330993 Slew rate control mechanism  
According to one embodiment a computer system is disclosed. The computer system includes a bus and a chipset coupled to the bus. The chipset detects the slew rate of a signal transmitted over the...
7330604 Model-based dewarping method and apparatus  
An apparatus and method for processing a captured image and, more particularly, for processing a captured image comprising a document. In one embodiment, an apparatus comprising a camera to capture...
7328362 Method and apparatus for selectively deskewing data traveling through a bus  
A method for selectively deskewing data traveling through a bus in a network device is disclosed. Bit-level data is received from each data line of a plurality of data lines of the bus. Vertical...
7328359 Technique to create link determinism  
A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency,...
7325153 Obtaining configuration data for a data processing apparatus  
A method to obtain configuration data for a data processing apparatus by calculating ( 110 ) a time interval between the commencement of a mode ( 104 ) and a subsequent event ( 108 ). The...
7325152 Synchronous signal generator  
A synchronous signal generator is provided that contains a first and second counting and delay circuit, which both are in a subhierarchical position with respect to a reset signal...
7315956 Method and apparatus for timing and event processing in wireless systems  
A digital baseband processor is provided for concurrent operation with different wireless systems. The digital baseband processor includes a digital signal processor for executing digital signal...
7308381 Timing verification method for semiconductor integrated circuit  
Initially, non-uniformity of statistical skews between a plurality of clock output terminal pairs is calculated. Next, a partial circuit driven by a clock output terminal pair having each skew...
7302601 Device and method for synchronizing an exchange of data with a remote member  
A device is provided for synchronizing, on a reference clock signal, an exchange of data with a remote member. The device includes a main variable delay line controlled by a first processing unit...
7296175 System on a chip bus with automatic pipeline stage insertion for timing closure  
A method of designing a system on a chip (SoC) to operate with varying latencies and frequencies. A layout of the chip is designed with specific placement of devices, including a bus controller,...
7296104 Automated calibration of I/O over a multi-variable eye window  
A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a...
7287176 Apparatus, method and storage medium for carrying out deskew among multiple lanes for use in division transmission of large-capacity data  
An apparatus, a method and a storage medium for carrying out a deskew among multiple lanes for use in a division transmission of large-capacity data. The method comprises the steps of detecting...
7284143 System and method for reducing clock skew  
In one embodiment, a method for balancing clock signals in a clock tree includes, at a register, receiving a divided input clock signal and a non-divided input clock signal and generating a first...
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