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9032239 HS-CAN bus clock recovery using a tracking oscillator circuit  
A method for recovering a clock frequency of a CAN bus, the method including: receiving a data signal, wherein the data signal includes at least one state transition; detecting the state...
9015212 System and method for exposing cloud stored data to a content delivery network  
A system for exposing data stored in a cloud computing system to a content delivery network provider includes a database configured to receive and store metadata about the data, the database being...
9009520 Closed-loop multiphase slew rate controller for signal drive in a computer system  
A slew rate controller for a computing system includes a slew rate control module, the slew rate control module further comprising a plurality of sampling modules, each sampling module...
9008196 Updating interface settings for an interface  
A computer system includes a processor, and the processor includes at least one interface for communicating with an electronic component. Each of the at least one interface has a set of interface...
9003221 Skew compensation for a stacked die  
An embodiment for skew compensation for a stacked die is disclosed. For an embodiment of an apparatus, an interposer has a first and a second integrated circuit die coupled to the interposer. The...
8984322 Device configured to switch a clock speed for multiple links running at different clock speeds and method for switching the clock speed  
A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality...
8977885 Programmable logic device data rate booster for digital signal processing  
A programmable logic device is provided that includes: a programmable interconnect adapted to route input signals through the device at a system clock rate; and a digital signal processor (DSP)...
8966309 Distribution of an incrementing count value  
Circuitry is disclosed that comprises: at least one element located within the circuitry and configured to hold an increasing count value; an encoder for receiving the increasing count value from...
8959380 Dynamically optimizing bus frequency of an inter-integrated circuit (‘I2C’) bus  
Optimizing an I2C bus frequency, the bus including signal lines coupling a master and slave nodes, a signal line coupled to a rise time detection circuit monitoring a voltage of the signal line,...
8959381 Method and system for clock offset and skew estimation  
This invention relates to methods and devices for clock offset and skew estimation. The invention has particular application in the alignment of slave clocks to a master clock. In embodiments of...
8959379 Thermal protection method for computer system and device thereof  
A thermal protection method for a computer system including at least a processor includes monitoring the temperature and loading of the processor via a system firmware in the computer system,...
8949652 Glitchless programmable clock shaper  
In one embodiment, a microprocessor includes one or more processing cores. At least one processing core includes a clock shaping circuit that is configured to receive a clock input signal. The...
8949648 System and method to overcome wander accumulation to achieve precision clock distribution over large networks  
A system and method for synchronizing clocks across a packet-switched network eliminates wander accumulation to enable precision clock distribution across a large network. In addition to standard...
8949681 Correction apparatus, correction method, and computer product  
A correction apparatus includes an acquirer that acquires the execution time of an instruction in a given block among a block group that includes blocks obtained by dividing program code; a...
8943351 USB based synchronization and timing system  
A synchronization apparatus, comprising: a USB device having a USB microcontroller, circuitry for observing USB traffic, and circuitry for decoding from a USB data stream a periodic data structure...
8938636 Generating globally coherent timestamps  
The present technology proposes techniques for generating globally coherent timestamps. This technology may allow distributed systems to causally order transactions without incurring various types...
8924765 Method and apparatus for low jitter distributed clock calibration  
A method and apparatus for generating an accurate clock generator timing source, comprising minimal jitter, excellent resolution, and an extended calibration range, for use, for example, in a...
8924766 Analysing timing paths for circuits formed of standard cells  
A method of performing and correcting a timing analysis performed by a data processing apparatus on a circuit formed of a plurality of cells to account for the reverse Miller effect. The timing...
8918667 Mesochronous signaling system with core-clock synchronization  
In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of...
8913705 Dynamic skew correction in a multi-lane communication link  
A mechanism for dynamic skew correction in a multi-lane communication link includes a receiver unit including, for each of the lanes, a first-in first-out (FIFO). The FIFO may store received...
8909974 Data processing apparatus, data processing method and recording medium  
A data processing apparatus comprising: a gate unit connected to an input or an output of a processing unit and configured to cut off the data input and output; a control unit configured to...
8907730 Frequency calibration device and method for programmable oscillator  
A frequency calibration method for a programmable oscillator includes the steps of: counting an oversampling number of an oversampling signal and estimating an accumulated bit number of a USB data...
8907711 Integrated circuit having latch circuits and using delay circuits to fetch data bits in synchronization with clock signals  
A semiconductor integrated circuit includes a delay circuit connected between a source of data bits and a data input terminal of a latch circuit. The delay circuit includes a first delay section...
8904217 System and method for managing power consumption in a computer device  
A system and method is disclosed for managing power consumption in a computing device. A policy controller determines whether an aggregated power consumption of a plurality of external interface...
8892932 Image forming apparatus and control apparatus  
The present image forming apparatus includes a first control unit and a second control unit driven by built-in clock oscillators to realize the distributed control. The first control unit...
8886988 Method of calibrating signal skews in MIPI and related transmission system  
In calibration mode, a clock signal and a data signal are respectively transmitted via a clock lane and a data lane of an MIPI. A test clock signal is provided by adjusting the phase of the clock...
8886987 Data processing unit and a method of processing data  
A data processing unit has a time information provider for processing a clock or a strobe signal, configured to provide a digitized clock or strobe time information on the basis of the clock or...
8885671 System for compensating for periodic noise in time interleaved system  
A system for compensating for periodic noise in a time interleaved system having multiple phases of interest includes a master clock path, a detection circuit and an actuator circuit. The master...
8881233 Resource management via periodic distributed time  
Systems and methods for providing resource management in a distributed network are disclosed. A loose collection of devices in a network may not be aware of the power restrictions for other...
8872566 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Integrated circuit having latch circuits and using delay circuits to fetch data bits in synchronization with clock signals
 
A semiconductor integrated circuit includes a delay circuit connected between a source of data bits and a data input terminal of a latch circuit. The delay circuit includes a first delay section...
8868962 Monitoring circuit and method  
A monitoring circuit for an integrated circuit comprises a non-temperature-inverted circuit and a temperature-inverted circuit. Operating parameters of the two circuits are measured, representing...
8867573 Transferring data between asynchronous clock domains  
A device comprises an integrated circuit having first and second domains, the first domain having a first clock boundary module; and the second domain having a second clock boundary module. The...
8856578 Integrated circuit device including skew adjustment circuit and skew adjustment method  
A skew adjustment circuit, provided in an integrated circuit device having a plurality of signal lines transmitting a plurality of signals respectively, and a plurality of buffer circuits to which...
8850259 Systems and methods for precise generation of phase variation in digital signals  
Systems and methods are disclosed for precise generation of phase variation in digital signals. The disclosed signal generation embodiments generate a pattern of information bits that represents a...
8843778 Dynamically calibrated DDR memory controller  
A method for calibrating a DDR memory controller is described. The method provides an optimum delay for a core clock delay element to produce an optimum capture clock signal. The method issues a...
8839021 Method for determining transmission error due to a crosstalk between signal lines by comparing tuning pattern signals sent in parallel from a memory device with the tuning pattern signals pre-stored in a host device  
A memory card includes a memory controller configured to perform control for sending and receiving a command signal, a response signal, a data signal, and a status signal in synchronization with a...
8839020 Dual mode clock/data recovery circuit  
A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The...
8838846 Autonomous, multi-channel USB data acquisition transducers  
A circuit and method of analog data acquisition synchronization from an analog sensor in multiple channels associated with a USB hub. An analog to digital converter connected to the sensor that is...
8839018 Programmable mechanism for optimizing a synchronous data bus  
An apparatus including a JTAG interface, synchronous bus optimizer, core clocks generator, synchronous strobe driver, and a DLL. The JTAG interface receives control information indicating a first...
8826062 Apparatus for synchronizing a data handover between a first clock domain and a second clock domain through phase synchronization  
An apparatus for synchronizing a data handover is disclosed. The calculator is clocked with a clock of a first clock domain and configured to provide synchronization pulse cycle duration...
8824615 Frequency tracing circuit and method thereof  
A frequency tracking circuit is disclosed. The frequency tracking circuit includes an edge selector, a phase-frequency processor and a digital controlled oscillator. The edge selector receives a...
8826059 Apparatus and method for buffering data between memory controller and DRAM  
A apparatus is provided for buffering data between a memory controller and a DRAM. The apparatus includes a phase locked loop (PLL), a phase interpolator for aligning a phase of an output clock...
8819475 Memory access circuit and memory access system  
According to one embodiment, a memory access circuit includes a PLL, a phy-clock tree, first, second, and master DLLs, and first and second PDs. The PLL generates a PLL output locked to a...
8819473 Clock integrated circuit  
The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more...
8812892 Hardware WCK2CK training engine using meta-EDC sweeping and adjustably accurate voting algorithm for clock phase detection  
One embodiment of the present invention sets forth a technique for performing high-performance clock training. One clock training sweep operation is performed to determine phase relationships for...
8812893 Apparatus and methods for low-skew channel bonding  
One embodiment relates an apparatus which includes a plurality of local synchronous divider circuits, each local synchronous divider circuit being configured to receive a serial clock signal and a...
8806262 Skew management in an interconnection system  
An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the...
8797868 Energy-efficient network device with coordinated scheduling and rate control using non-zero base power  
A network device of a communication network is configured to implement coordinated scheduling and processor rate control. In one aspect, packets are received in the network device and scheduled...
8799545 Restoring stability to an unstable bus  
A method for restoring stability to an unstable bus includes cycling a clock of the bus a number of times, transmitting a stop bit, cycling a clock line of the bus at least one time and...
8797083 Methods of operating timers to inhibit timing error accumulation  
Methods of operating timers include generating a periodic timing signal having a first frequency that differs from a desired timer frequency (1 KHz) by a first amount. This periodic timing signal...