Patents in Class 713/503

Matches 1 - 50 out of 632

Match	Document	Document Title
1	7624310	System and method for initializing a memory system, and memory device and processor-based system using same Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read...
2	7620839	Jitter tolerant delay-locked loop circuit Systems and methods are disclosed herein to provide improved jitter tolerant delay-locked loop circuitry. For example, in accordance with an embodiment of the present invention, an integrated...
3	7620837	Data transmission system and data transmission apparatus A data transmission system including a slave device ( 30 ) and a master device ( 10 ) is disclosed. Slave device ( 30 ) may include a slave side clock signal generator section ( 32 ) for generating...
4	7620836	Technique for synchronizing network devices in an access data network A master clock reference signal may be provided to selected packet fiber nodes in order to synchronize the local clock reference signals generated at selected devices in a cable network. In this...
5	7617410	Simultaneously updating logical time of day (TOD) clocks for multiple cpus in response to detecting a carry at a pre-determined bit position of a physical clock A system, method and computer program product for synchronizing adjustment of a time of day (TOD) clock for a computer system having multiple CPUs, each CPU having an associated physical clock...
6	7617409	System for checking clock-signal correspondence A data processing system is provided having a clock signal comparator comprising a reference input port for receiving a reference clock signal and at least a further input port for receiving...
7	7610504	Semiconductor integrated circuit A semiconductor integrated circuit including a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region...
8	7610503	Methods for generating a delayed clock signal An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock...
9	7600145	Clustered variations-aware architecture Methods and apparatus to provide a clustered variations-aware architecture are described. In one embodiment, one or more variations within a clock domain are detected and utilized to adjust a clock...
10	7600144	Data transmission error reduction via automatic data sampling timing adjustment A data transmission error reduction circuit is formed including a delay circuit, a detection circuit and a control circuit. In one embodiment, the delay circuit includes n delay element and...
11	7599459	Receiving apparatus, data transmission system and receiving method A receiving apparatus receives data sequences, each of which includes plural data blocks, from plural transmission lines, respectively. The apparatus includes plural elastic buffers and a deskew...
12	7590789	Optimizing clock crossing and data path latency In one embodiment, the present invention includes a method for transmitting a predetermined data pattern from a first agent to a second agent of an interface, receiving an indication of correct...
13	7584310	Signal processing device A signal processing device includes a start time obtaining part that obtains a start time when a predetermined process is started in response to an interrupt request associated with a valid edge of...
14	7571340	Eliminating receiver clock drift caused by voltage and temperature change in a high-speed I/O system that uses a forwarded clock Integrated circuits include clock deskew circuitry. The clock deskew circuitry, at the receiver side, receives data signals and a forwarded clock signal from a transmitter. The receiver detects a...
15	7571339	Clock recovery system with triggered phase error measurement A measurement system includes a clock recovery system and a measurement module coupled to the clock recovery system. The clock recovery system has an associated response characteristic. The clock...
16	7571338	Determining a time difference between first and second clock domains Buffer circuitry receives data to be processed by electronic circuitry using a first clock signal associated with a first clock domain. The buffered data is output using a second clock signal...
17	7571267	Core clock alignment circuits that utilize clock phase learning operations to achieve accurate clocking of data derived from serial data streams having different relative skews Core clock alignment circuits include a serial-in parallel-out (SIPO) data processing circuit, which is configured to generate a plurality of lanes of deserialized data in response to a...
18	7568118	Deterministic operation of an input/output interface In one embodiment, the present invention includes a method for receiving data from a second device in a first device, forwarding the data from an input/output (I/O) clock domain to a system clock...
19	7562247	Providing independent clock failover for scalable blade servers Methods and systems are disclosed for providing independent clock failover for scalable blade servers that include assigning a server blade to one of a plurality of clock failover groups, providing...
20	7562246	Phase controllable multichannel signal generator A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second...
21	7558979	Methods for determining simultaneous switching induced data output timing skew A method of determining timing skew between data outputs of a memory device can include writing a predetermined data pattern to a memory device at a first operational frequency that is less than a...
22	7555668	DRAM interface circuits that support fast deskew calibration and methods of operating same A DRAM interface circuit includes a clock generation circuit configured to generate a plurality of internal clock signals and skew data in response to a plurality of data strobe signals (DQS)...
23	7555667	Programmable logic device integrated circuit with dynamic phase alignment capabilities and shared phase-locked-loop circuitry Adjustable transceiver circuitry is provided for programmable integrated circuits. The transceiver circuitry has a dynamic phase alignment circuit that can be used for aligning clock and data...
24	7555086	Plural circuit selection using role reversing control inputs Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication...
25	7549074	Content deskewing for multichannel synchronization The various embodiments of the invention provide an apparatus, system and method for data content deskewing among a plurality of data channels for data synchronization. The various embodiments...
26	7543202	Test apparatus, adjustment apparatus, adjustment method and adjustment program A test apparatus that test a device under test includes a plurality of signal input/output units each of which has a signal output section and a signal input section that: firstly, adjusts each of...
27	7542532	Data transmission device and input/output interface circuit A clock generator supplies a clock signal to a data transmission circuit for a jitter resistance test of a data transmission/reception circuit, while supplying a clock signal to a data reception...
28	7533285	Synchronizing link delay measurement over serial links Systems, methods, and other embodiments associated with synchronizing link delay is provided. In one example system, a system for synchronizing signal communication between a first electronic...
29	7526666	Derived clock synchronization for reduced skew and jitter Two or more circuits (e.g. processing cores of a graphics processor) operate synchronously at a fast clock frequency. A core interface to each of the processing cores is designed to communicate in...
30	7526664	Drift tracking feedback for communication channels A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A...
31	7519845	Software-based audio rendering Software-based audio rendering is described. A particular implementation includes computer readable media configured to measure a first drift rate between an external clock and an audio clock until...
32	7519844	PVT drift compensation A timing circuit for generating a timing signal having a predetermined relationship with a reference signal. The timing circuit includes a locked loop for generating the recovered clock signal,...
33	7519139	Signal monitoring systems and methods Systems and methods are disclosed herein to provide signal monitoring techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a phase...
34	7512827	Dual module clock supply for CAN communication module A CAN communication module ( 10 ) comprising a protocol kernel ( 14 ) and a CAN logic block ( 12 ) is provided. The protocol kernel includes a CAN bus interface and the CAN logic block includes a...
35	7506193	Systems and methods for overcoming part to part skew in a substrate-mounted circuit Variable compensation for part to part skew of components in a substrate-mounted circuit is described. The variability may be provided through a computer software program acting on a programmable...
36	7502815	True random number generator and method of generating true random numbers A true random number generator may comprise a multi-gigabit transceiver with a transceiver to receive a signal of predetermined source data. Recovery circuitry of the transceiver may be operable to...
37	7500131	Training pattern based de-skew mechanism and frame alignment Some embodiments of the invention provide a training sequence that may be used in a deskewing process or a protocol to be implemented in a training sequence deskew. Embodiments may also comprise a...
38	7500130	Cycle-accurate real-time clocks and methods to operate the same Cycle-accurate real-time clocks and methods to operate the same are disclosed. An example real-time clock comprises a first counter to count cycles of a selectively-operable clock, a multiplexer to...
39	7496781	Timing signal generating circuit with a master circuit and slave circuits A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying...
40	7496780	Reduction of data skew in parallel processing circuits Signal processing circuitry having parallel processing channels has clock-generation circuitry that generates (i) high-speed clock signals used to drive the channels and (ii) synchronization...
41	7493510	Clock signal generator circuit for serial bus communication Provided is a smart card for communicating with a host computer through a universal serial bus (USB). The smart card includes an internal clock signal generator to generate an internal clock...
42	7490187	Hypertransport/SPI-4 interface supporting configurable deskewing A memory system having a memory controller and a daisy chain of memory chips. The memory controller is coupled to memory chips in the daisy chain of memory chips by an address/command bus chain....
43	7487378	Asymmetrical IO method and system An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources...
44	7486754	System clock distributing apparatus and system clock distributing method To provide a system clock distributing apparatus and a system clock distributing method for reducing a skew of a system clock and a synchronizing signal at low cost. The system clock distributing...
45	7478255	Clock distribution in multi-cell computing systems Embodiments of the invention relate to distribution of clocks to CPUs in processing cells of a multi-cell system. In an embodiment, each cell includes an interface, referred to as an agent. A...
46	7475272	Method for calculating clock offset and skew Disclosed is a method for calculating clock offset and skew between two clocks in a computer system. The method comprises the steps of sending data packets from a first processing unit in the...
47	7472305	Method and apparatus for limiting the output frequency of an on-chip clock generator Apparatus for limiting an output signal frequency of an on-chip clock generator is presented. Electronic circuitry compares the value of a ratio between the internal clock signal frequency and the...
48	7469354	Circuit including a deskew circuit for asymmetrically delaying rising and falling edges A circuit including a deskew circuit. The deskew circuit is configured to receive a first signal having a first edge delayed from a second edge of a second signal by a first delay and a third edge...
49	7466723	Various methods and apparatuses for lane to lane deskewing Various methods, apparatuses and systems are described in which a skew delay time between communication lanes is determined. A data transfer path is established which includes two or more...
50	7464286	Programmable logic devices with skewed clocking signals A programmable logic device has programmable phase-shifting circuitry. The phase-shifting circuitry is used to generate a set of skewed clock signals that is used to adjust the relative timing of...

Matches 1 - 50 out of 632

1 2 3 4 5 6 7 8 9 10 11 12 13 >