Matches 151 - 200 out of 606 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >
Match Document Document Title
7058840 Method and apparatus for generating a second signal having a clock based on a second clock from a first signal having a first clock  
An apparatus for generating a second signal having a clock based on a second clock from a first signal with a first clock comprises first and second means for sampling the first signal to determine...
7055050 Network synchronization technique  
A network synchronization method allows reduced frequency fluctuations due to synchronization control in a network. Each node connected to the network has time information individually varying in a...
7051225 Memory system, module and register  
Disclosed are a memory command address system and a memory module that can be operated not only for 266 MHzCLK but also for 200 MHzCLK, in which clock timings in the input sections of a PLL, a...
7047384 Method and apparatus for dynamic timing of memory interface signals  
A method and apparatus for using different timings to latch signals sent by two memory devices of identical design to compensate for differences in the lengths of conductors across which the...
7043657 Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle  
A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction...
7043656 Methods and apparatus for extending a phase on an interconnect  
Interconnect logic performs a transaction on an interconnect. The transaction may include multiple phases and the interconnect logic may include a counter state machine coupled to an interconnect...
7043654 Selecting a first clock signal based on a comparison between a selected first clock signal and a second clock signal  
According to some embodiments, a potential clock signal is selected based on a comparison between a selected first clock signal and a second clock signal.
7043653 Method and apparatus for synchronous signal transmission between at least two logic or memory components  
An internal clock signal of a logic/memory component that receives signals is transmitted as a reference clock to a transmitting logic/memory component. With the aid of the reference clock, the...
7043652 Calibration method and memory system  
In a memory system having a memory controller 20 and at least one DRAM 30 , the memory controller 20 receives a continuous and alternate inversion signal as a pseudo clock signal from the DRAM...
7036037 Multi-bit deskewing of bus signals using a training pattern  
A method for multi-bit de-skewing of parallel bus signals is disclosed. The method includes receiving data comprising a multi-bit word and a training pattern. After a first control word of the...
7032122 Data transfer system capable of transferring data at high transfer speed  
A first feature of a data processing system is in that, in a data transfer path including a plurality of signal lines used for data transfer, a phase control is performed independently for each of...
7028210 System and method for automatically correcting timers  
As provided, a system and method for automatically correcting timers to improve timing accuracy. The system and method provides for the use of inexpensive low tolerance resonators or oscillators...
7028205 Techniques to monitor transition density of an input signal  
Techniques to determine and indicate the extent to which transitions of an input signal deviate from a desired transition region. In an implementation, an indication may be provided when a...
7024577 Program logic device for synchronous operation with multiple clock signals  
An object of the present invention is to provide a programmable logic device capable of exchanging information with a logic constitution connected to a control processor and operating synchronously...
7020794 Interleaved delay line for phase locked and delay locked loops  
An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and...
7020793 Circuit for aligning signal with reference signal  
A signal-aligning circuit includes a phase-adjusting circuit, a first control circuit, a second control circuit, and a tuning circuit. The first control circuit outputs a first voltage signal...
7017070 Apparatus for synchronization of double data rate signaling  
A signal phase shifting circuit shifts the phase of an input signal, such as a STROBE signal, based on a reference signal, such as a CLOCK signal, to facilitate, for example, receiving of double...
7017069 PWM control circuit, microcomputer and electronic equipment  
A PWM control circuit, microcomputer and electronic equipment which can generate high-resolution PWM signals through a small-sized scale of circuit. The PWM control circuit includes a PWM period...
7017068 Adaptive clock skew in a variably loaded memory bus  
The preferred embodiments of the present invention are directed to the selective phase lag and time delay of clock signals within a computer system to compensate for additional parasitic...
7017067 Method and bus system for synchronizing a data exchange between a data source and a control device  
A method for synchronizing a data exchange between a data source and a control device is provided. A synchronization request signal is first transmitted via the bus system to the data source, which...
7017064 Calculating apparatus having a plurality of stages  
A calculating apparatus, or system, having a plurality of stages, such as in a pipeline arrangement, has the clocking rail or conductor positioned alongside the stages. With a large number, i.e.,...
7016769 Control device for controlling/regulating the operational sequences in a motor vehicle, and a method of starting such a control device  
A control device and a method for controlling and/or regulating the operational sequences in a motor vehicle, and a method for starting such a control device, which provide a program in a storage...
7013407 Method, apparatus, and system for high speed data transfer between electronic devices  
According to one aspect of the invention, a method is provided in which a plurality of data signals are transmitted in parallel mode via a parallel bus from a first device to a second device. Phase...
7012474 System and method generating a delayed clock output  
The system and method generates two clock signals, one with a 2 ns delay with respect to the other, from a single PLL to enable a RGMII.
7010621 System having a spread-spectrum clock for further suppression of electromagnetic emissions in network devices communicating via a network bus  
A network system includes a network having a network bus, such as unshielded differential twisted-pair wires, electrically connected to a plurality of remote devices, and a network controller for...
7003686 Interface circuit  
An interface circuit according to one embodiment of the present invention includes a clock signal, a first phase locked loop coupled to the clock signal line and generating a reference clock...
7003684 Memory control chip, control method and control circuit  
A memory control chip, control method and control circuit. Instead of accessing a plurality of memory modules in a memory bank by referencing the same clocking signal, each memory module references...
6996738 Robust and scalable de-skew method for data path skew control  
A method for selectively deskewing data traveling through a bus in a network device is disclosed. Bit-level data is received from each data line of a plurality of data lines of the bus. Vertical...
6993673 Apparatus for frequency and timing recovery in a communication device  
Apparatus for recovering timing of data input to a receiver, the apparatus consisting of an interpolator which receives the input data and generates interpolated-data in response to an...
6983394 Method and apparatus for clock signal performance measurement  
Method and apparatus for providing a measure of jitter and skew of a clock signal is described. The clock signal may be used as an input to a digital circuit. In one embodiment, a digital delay...
6981169 Modified glitch latch for use with power saving dynamic register file structures  
In the Retirement Payload Array (RPA) of a microprocessor, the signal “READ” is logically combined with the primary clock signal “CLK” in a control circuit of a modified glitch latch such...
6981168 Clock data recovery system  
A clock data recovery system is provided for resampling a clock signal according to an incoming data signal stream. It comprises a clock generator for generating said clock signal wherein one of...
6976184 Clock forward initialization and reset signaling technique  
A system and method for initializing and resetting a clocking subsystem having a phased locked loop (PLL) within an input/output interface of a data processing system. A first timer generates...
RE38903 Method and apparatus for generating a pulse  
A circuit for generating a pulse with minimal delay after receiving a trigger signal includes a passgate, a gating circuit, and a reset circuit. The passgate is enabled by control signals received...
6971040 Method and system for reducing the effects of simultaneously switching outputs  
A delay element is coupled to a first interface, which is coupled to a second interface via interconnect. Traces in the interconnect for propagating output signals from the first interface to the...
6970526 Controlling the system time clock of an MPEG decoder  
During decoding and processing of program clock reference (PCR) values in MPEG-2 transport streams, a first initial difference value is obtained by calculating a difference between a first detected...
6968436 Memory controller that controls supply timing of read data  
A method for supplying a data signal read from a memory to an internal circuit of a semiconductor integrated circuit is described. First, supply timing information determining supply timing of the...
6966021 Method and apparatus for at-speed testing of digital circuits  
A scheme for multi-frequency at-speed logic Built-In Self Test (BIST) is provided. This scheme allows at-speed testing of very high frequency integrated circuits controlled by a clock signal...
6963992 Method and apparatus to generate clock and control signals for over-clocking recovery in a PLL  
An apparatus comprising a circuit that may be configured to (i) change a frequency of one or more first signals in response to a second signal and (ii) generate a third signal in response to either...
6963989 Method and apparatus for adjusting data hold timing of an output circuit  
A method and apparatus are disclosed for adjusting the individual data hold time of data output buffers. Clock signals for the output buffers are respectively and individually adjusted for each of...
6961862 Drift tracking feedback for communication channels  
A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A...
6961861 Globally clocked interfaces having reduced data path length  
A interface, which connects memory and an integrated circuit, having a write path and read path that allow synchronous data propagation is provided. Further, a method for synchronizing data...
6961799 Method of detecting a source strobe event using change detection  
A hub based computer system having a central hub that communicates with a plurality of satellite devices over respective link buses. Each link bus is substantially the same and adheres to a...
6959397 Programmable skew clock signal generator selecting one of a plurality of delayed reference clock signals in response to a phase accumulator output  
A programmable skew clock signal generator has a frequency generator circuit ( 104 ) consistent with the invention produces an output signal F φ0 from a reference signal F ref A frequency...
6959396 Method and apparatus for reducing clock skew in an integrated circuit  
A method is provided to reduce clock skew in an integrated circuit having a number of circuit blocks, which comprises the following steps. A first source clock coupled to a clock input terminal of...
6957357 Clock synchronization with removal of clock skews through network measurements in derivation of a convext hull  
A method, computer program product, and data processing system for estimating and correcting the amount of clock skew in end-to-end network timing measurements is disclosed. Measured delays are...
6956908 Technique to simultaneously distribute clock signals and data on integrated circuits, interposers, and circuit boards  
A technique is described for simultaneously and synchronously transmitting digital data and a clock signal in a digital integrated circuit, circuit board, or system. The technique is based on the...
6954871 Method of matching different signal propagation times between a controller and at least two processing units, and a computer system  
In a fast synchronously controlled computer system, data signals are called from various memory banks, and this can result in propagation times of different lengths for the data signals, depending...
6952791 Method and circuit for initializing a de-skewing buffer in a clock forwarded system  
A method and circuit for initializing a buffer in a clock forwarded system. A buffer is configured for temporarily storing incoming data received on the clock-forwarded interface. The buffer may...
6952790 System for varying timing between source and data signals in a source synchronous interface  
A system for measuring timing margins in an interface between a core and an input/output device on a chipset. In order to measure the amount of available variation in data and strobe signals, delay...
Matches 151 - 200 out of 606 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >