Match Document Document Title
9037894 Devices and methods using supervisor chips (integrated circuits) to generate time acceptance windows  
Timing circuits including supervisor chip(s), capacitors, and latches. The supervisor chip(s) and capacitors cooperate to generate an electrical signal (window signal) having a high logic state...
9032238 Systems and methods for crossover delay to prevent power module faults  
Systems and methods detect when a transition from a first power module to a second power module is taking place and generates a lockout pulse when the transition is detected. The lockout pulse...
9032239 HS-CAN bus clock recovery using a tracking oscillator circuit  
A method for recovering a clock frequency of a CAN bus, the method including: receiving a data signal, wherein the data signal includes at least one state transition; detecting the state...
9021293 Methods for operating a memory interface circuit including calibration for CAS latency compensation in a plurality of byte lanes  
A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface...
9021292 Method and system for asynchronous serial communication in a ring network by generating an oversampling clock using a fractional rate multiplier and sampling a received data bit sequence that includes voltage and temperature information in a battery management system  
Systems and methods are disclosed which relate to improving synchronization of clocks between a sender and a receiver communicating via an asynchronous serial interface. In a ring topology, a...
RE45487 Processor having execution core sections operating at different clock rates  
A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations...
8996906 Clock management block  
A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple...
8984322 Device configured to switch a clock speed for multiple links running at different clock speeds and method for switching the clock speed  
A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality...
8984321 Jitter reduction method and apparatus for synchronised USB devices  
A method of reducing jitter in a local clock of a synchronised USB device attached to a USB Hub, the USB Hub having a local clock and repeater circuitry, comprising: observing a USB data stream...
8977884 Shared-PLL audio clock recovery in multimedia interfaces  
A bit stream includes playback data having an associated clock rate and a variable reference clock that is synchronized to the bit stream. A playback clock recovery signal and a data recovery...
8966308 System and method for clock domain management  
A source clock system clock domain is selected by communication of the desired clock domain from a receiver clock system through a clock line, such as through a clock differential pair. For...
8966151 Apparatus and method for a reduced pin count (RPC) memory bus interface including a read data strobe signal  
A method and apparatus for a memory bus interface including a read data strobe. The interface includes a chip select for delivering a chip select signal that indicates when a peripheral device is...
8966309 Distribution of an incrementing count value  
Circuitry is disclosed that comprises: at least one element located within the circuitry and configured to hold an increasing count value; an encoder for receiving the increasing count value from...
8959378 Output timing control circuit and semiconductor apparatus using the same  
An output timing control circuit of a semiconductor apparatus includes a delay amount counter block configured to count a delay amount of an output reset pulse signal based on an external clock...
8959379 Thermal protection method for computer system and device thereof  
A thermal protection method for a computer system including at least a processor includes monitoring the temperature and loading of the processor via a system firmware in the computer system,...
8949651 Multiple clock domain cycle skipping utilizing optimal mask to minimize voltage noise  
Implementations of the present disclosure involve an apparatus and/or method for providing one or more clock signals that include a skipped clock cycle to a portion of a computing system. The...
8935558 Overclocking module, a computer system and a method for overclocking  
An overclocking module, a computer system and a method for overclocking are provided. The method is used to overclock the computer system. The overclocking module of the invention includes a...
8930737 Method and devices for controlling operations of a central processing unit  
Provided is a method in a control circuitry controlling the operations of a central processing unit, CPU. The CPU is associated with a nominal clock frequency. The CPU is further coupled to an I/O...
8930741 Voltage regulator with drive override  
Techniques to enable voltage regulators to adjust for coming load changes are presented herein. In some embodiments, a functional block such as a microprocessor core having an associated clock...
8930742 Clock signals for dynamic reconfiguration of communication link bundles  
In at least some embodiments, an electronic device includes a processor and a memory coupled to the processor. The electronic device also includes a serial communication link controller coupled to...
8930739 Memory controller  
A memory controller includes an digitally programmable delay unit having a selectable delay time receiving a read-enable signal and outputting a delayed read-enable signal. The delay time is...
8924765 Method and apparatus for low jitter distributed clock calibration  
A method and apparatus for generating an accurate clock generator timing source, comprising minimal jitter, excellent resolution, and an extended calibration range, for use, for example, in a...
8918667 Mesochronous signaling system with core-clock synchronization  
In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of...
8918669 Mesochronous signaling system with clock-stopped low power mode  
In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of...
8909974 Data processing apparatus, data processing method and recording medium  
A data processing apparatus comprising: a gate unit connected to an input or an output of a processing unit and configured to cut off the data input and output; a control unit configured to...
8904255 Integrated circuit having clock gating circuitry responsive to scan shift control signal  
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality...
8898503 Low latency data transfer between clock domains operated in various synchronization modes  
Transferring data from a first clock domain to a second clock domain, wherein the second clock domain has a fixed clock frequency, and the first clock domain has a variable clock frequency. The...
8892935 Dynamic bus clock rate adjusting method and device  
A dynamic bus clock rate adjusting method is to be executed by a bus controller and a CPU. The bus controller is coupled with a bus that is coupled with a plurality of slave devices. The method...
8880833 System and method for read synchronization of memory modules  
A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to...
8869152 Methods and procedures to dynamically adjust processor frequency  
A method for altering an operating frequency of a processor. The method includes monitoring a real-time performance indicator of a system, and determining a desired frequency in response to the...
8868827 FIFO apparatus for the boundary of clock trees and method thereof  
A FIFO apparatus uses a first clock signal in a first clock domain to receive an input signal and uses a second clock signal in a second clock domain to output an output signal. An example...
8862926 Hardware controlled PLL switching  
A system and method for efficiently managing multiple PLLs on a system on a chip (SOC). A SOC includes a hardware phase lock loop (PLL) switching control block coupled to a software interface. The...
8839019 Semiconductor apparatus for controlling a frequency change of an internal clock  
A semiconductor apparatus includes a clock frequency change block configured to output a plurality of internal clocks with different frequencies by dividing a frequency of an external clock in...
8839018 Programmable mechanism for optimizing a synchronous data bus  
An apparatus including a JTAG interface, synchronous bus optimizer, core clocks generator, synchronous strobe driver, and a DLL. The JTAG interface receives control information indicating a first...
8832487 High-speed I/O data system  
In embodiments of a high-speed I/O data system, a first computer chip includes a data transmission system, and a second computer chip includes a data reception system. A data channel communicates...
8806257 Image processing apparatus and control method thereof  
Disclosed is an image processing apparatus, which can differently set a clock ratio according to a use rate of a CPU, and a control method thereof. The image processing apparatus may include a...
8806496 Virtualizing a processor time counter during migration of virtual machine by determining a scaling factor at the destination platform  
In one embodiment, the present invention includes a method for determining a scaling factor between a frequency of a first processor and a frequency of a second processor after a guest software is...
8799699 Data processing system  
Each of a plurality of master devices outputs a speed grade signal indicating a data transfer speed with a data transfer request. An arbiter arbitrates transfer requests and speed grade signals...
8797083 Methods of operating timers to inhibit timing error accumulation  
Methods of operating timers include generating a periodic timing signal having a first frequency that differs from a desired timer frequency (1 KHz) by a first amount. This periodic timing signal...
8782458 System and method of data communications between electronic devices  
A system and method of data communications between a first device and a second device is disclosed. The method includes generating a first clock signal at the first device and generating a second...
8775856 System and method for generating clock signal for a plurality of communication ports by selectively dividing a reference clock signal with a plurality of ratios  
Various techniques are provided to generate a plurality of reference clock signals using a single reference clock signal generator. In one example, a clock signal generation system includes a...
8775857 Sequential on-chip clock controller with dynamic bypass for multi-clock domain testing  
A controller includes a clock control unit configured to provide a first output to test circuitry and a bypass unit configured to provide a second output to a further controller. The controller is...
8775853 Device and method for preventing lost synchronization  
A method for synchronizing two connection nodes by a reception node of the connection nodes with a clock data recovery circuit that generates a synchronization clock from input data. The method...
8762763 Single-wire transmission interface and method of transmission through single-wire  
The present invention discloses a single-wire transmission interface, and a method of transmission through single-wire. The method comprises: providing a single-wire signal through a single-wire;...
8762765 Electronic apparatus, clock apparatus, and clock control apparatus  
An electronic apparatus input and/or output a signal from and/or an external apparatus. The electronic apparatus includes: a clock section in which a frequency is set and which gives a clock...
8756446 Microprocessor having a low-power mode and a non-low power mode, data processing system and computer program product  
A microprocessor has a low-power mode and a non-low power mode. The microprocessor includes a processor core for executing instructions provided to the microprocessor and a clock providing a clock...
8756451 Frequency synthesis methods and systems  
Multi-tier methods and systems to synthesize a reference frequency, and control one or more tiers in view of multiple prioritized criteria. A first tier of a frequency synthesizer may include a...
8751854 Processor core clock rate selection  
Techniques described herein generally relate to multi-core processors including two or more processor cores. Example embodiments may set forth devices, methods, and computer programs related to...
8751852 Programmable mechanism for delayed synchronous data reception  
An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, and a...
8751851 Programmable mechanism for synchronous strobe advance  
An apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, a core clocks generator, and a synchronous strobe driver. The JTAG interface is configured to receive...