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7415625 Policy table rule based processor side bus signaling  
A system and method for selecting a computer hardware component of a computing system to throttle based on a selection policy is disclosed. A co-thermal control system may receive a first signal...
7403122 RFID tag circuits operable at different speeds  
Embodiments of RFID tag circuits and methods are described, which include a chip having a clock circuit operable to generate a clock signal having different frequencies, and one or more components...
7400945 On-die temperature monitoring in semiconductor devices to limit activity overload  
Thermal control for a controller in a data processing environment is described. In one embodiment, the invention includes detecting a temperature of a semiconductor device at a thermal sensor on...
7398406 Data processor  
It is aimed at providing a data processor capable of suppressing a sudden current change from the viewpoint of a synchronization clock. A data processor 1 comprises a clock pulse generation...
7395398 Memory controller that selectively changes frequency of a memory clock signal, a smart card including the same, and a method of controlling a read operation of a memory  
Provided are a memory controller that selectively changes a frequency of a memory clock signal, a smart card including the memory controller, and a method of controlling a read operation of a...
7386634 Control method for bus provided with internal switch  
In a bus, which is provided with a switch having a plurality of master ports and a plurality of slave ports and can connect each of the plurality of master ports to an arbitrary port of the...
7380152 Daisy chained multi-device system and operating method  
A multi-device system having a daisy chain system bus structure and related method of operation are disclosed. A reference signal having a defined oscillation period is communicated around the...
7380153 Micropipeline stage controller and control scheme  
A technique for controlling local events in two-phase asynchronous handshake circuits.
7376856 Circuit arrangement  
An object of the present invention is to provide a circuit device in which the power consumption can be reduced without the dedicated signal. A circuit device (1) comprising a D flip-flop (F0) for...
7370221 CPU frequency adjusting system and method  
A Central Processing Unit (CPU) frequency adjusting system has a multi-level architecture including an application level, a driver level, a hardware abstraction level, and a hardware platform. The...
7366938 Reset in a system-on-chip circuit  
An electronic device having first circuitry operating in a first clock environment and second circuitry operating in a second clock environment, the first circuitry being arranged to generate a...
7366943 Low-latency synchronous-mode sync buffer circuitry having programmable margin  
Synchronization is attained between a source clock domain and a target clock domain of arbitrary frequency ratios and each of which periodically has edges nominally aligned to edges of a reference...
7366937 Fast synchronization of a number of digital clocks  
The present invention relates to a method for synchronizing a number of digital clocks to a synchronizing signal, said method comprising generating centrally a reference clock, synthesizing said...
7366931 Memory modules that receive clock information and are placed in a low power state  
Embodiments described herein provide a power saving state for a memory system. For example, a memory system may derive clocking information from a training pattern sent over a memory channel. A...
7360109 Measuring the interval of a signal using a counter and providing the value to a processor  
The present invention aims to be capable of properly measuring the cycle of an external signal even where a timer clock and a CPU clock are operated asynchronously. A timer circuit comprises a...
7353421 Method and apparatus for determining and allocating clock frequencies for plurality of processing units on system start-up or resetting of the system  
A method and apparatus for operating a computer system comprising a first and a second computing unit, the method comprising selecting a first clock frequency for operation of said first computing...
7350096 Circuit to reduce power supply fluctuations in high frequency/ high power circuits  
The present invention provides for a circuit for transitioning clocking speeds. A counter is coupled to the clocking means. A comparator is coupled to an output of the counter. A first divider is...
7349762 Systems and methods for thermal management  
Systems and methods for sensing temperatures of multiple functional blocks within a digital device and controlling the operation of these functional blocks in a manner that selectively reduces...
7346795 Delaying lanes in order to align all lanes crossing between two clock domains  
In some embodiments an apparatus and method may comprise a plurality of lanes between two clock domains, each lane comprising circuitry to generate a first signal when the lane may lose cycle...
7340633 Method for automatically detecting the clock frequency of a system clock pulse for the configuration of a peripheral device  
The present invention provides a method for automatic identification of the clock frequency of a system clock (15) for the configuration of a peripheral device (12), having the following steps:...
7340629 Method and system for application-based normalization of processor clocks in a multiprocessor environment  
A method is presented for enabling application-level software to normalize processor clock values within a multiprocessor data processing system. A first processor number associated with a first...
7334148 Optimization of integrated circuit device I/O bus timing  
The invention includes a method to adjust integrated circuit device I/O bus timing. In one embodiment, the method includes comparing an alignment between an edge of a first clock signal to a...
7334151 Method of and device for detecting cable connection using an oscillation circuit and a counter  
The detector includes the plug for connecting the personal computer through a cable, battery power supply which provides a constant power supply, and the MCU which receives a specific potential...
7334152 Clock switching circuit  
A clock switching circuit comprises: a composite clock generation circuit, which is to receive a first clock, a second clock, and a clock switching execution signal for switching between the first...
7328360 Maintaining synchronization of multiple data channels with a common clock signal  
Maintaining synchronization when sending/receiving multiple channels of data with a corresponding common reference clock signal. Synchronization signals (e.g., pulses) are generated periodically...
7328359 Technique to create link determinism  
A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency,...
7325152 Synchronous signal generator  
A synchronous signal generator is provided that contains a first and second counting and delay circuit, which both are in a subhierarchical position with respect to a reset signal...
7325153 Obtaining configuration data for a data processing apparatus  
A method to obtain configuration data for a data processing apparatus by calculating (110) a time interval between the commencement of a mode (104) and a subsequent event (108). The calculated...
7315928 Apparatus and related method for accessing page mode flash memory  
A method of controlling an access time for accessing a flash memory comprises comparing a target address of the flash memory with an address of the flash memory that was previously accessed;...
7315957 Method of providing a second clock while changing a first supplied clock frequency then supplying the changed first clock  
Methods, circuits, and apparatus for changing a frequency of a clock signal provided to a graphics memory while reducing any resulting visual glitch or disturbance on a monitor. A specific...
RE39963 System and method for dynamic clock generation  
An application specific integrated circuit (ASIC) has a clock controller that dynamically selects an appropriate clock frequency for a resource. The ASIC includes a central processing unit (CPU),...
7307550 Decoding method, decoding device, and program for the same  
To provide a decoding method and a decoding device capable of reducing a power consumption in a decoding processing and a program for the same. The decoding method to be executed by a decoding...
7305575 Interface circuit that interconnects a media access controller and an optical line termination transceiver module  
A communication system includes an interface that allows a media access controller (MAC) and an optical line termination transceiver module (TM), which have incompatible interfaces, to be...
7302601 Device and method for synchronizing an exchange of data with a remote member  
A device is provided for synchronizing, on a reference clock signal, an exchange of data with a remote member. The device includes a main variable delay line controlled by a first processing unit...
7299374 Clock control method and apparatus for a memory array  
A clock control method and apparatus are provided employing a clock control circuit which generates an array clock for a memory array from a system clock and a reset control signal. The reset...
7296173 Semiconductor integrated circuit  
A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different...
7296176 Method and apparatus for limiting the number of asynchronous events that occur during a clock cycle  
One embodiment of the present invention provides a system that limits a maximum repetition rate of an asynchronous circuit. The system operates by receiving a clock signal at a rate-controlling...
7296175 System on a chip bus with automatic pipeline stage insertion for timing closure  
A method of designing a system on a chip (SoC) to operate with varying latencies and frequencies. A layout of the chip is designed with specific placement of devices, including a bus controller,...
7290161 Reducing CPU and bus power when running in power-save modes  
A processing system includes a bus and a processor whose core is constrained to have one or more core clock signal frequencies no lower than a predetermined multiple of the lowest of one or more...
7284143 System and method for reducing clock skew  
In one embodiment, a method for balancing clock signals in a clock tree includes, at a register, receiving a divided input clock signal and a non-divided input clock signal and generating a first...
7280628 Data capture for a source synchronous interface  
Method and apparatus for data recapture from a source synchronous interface. A data signal is obtained via the source synchronous interface. A timing signal is obtained via the source synchronous...
7278043 System, method, and apparatus for overload detection in real-time data processing applications  
A method for overload detection according to one embodiment of the invention includes a control process and a data process. In response to a timing signal, the control process sets a state of a...
7278047 Providing different clock frequencies for different interfaces of a device  
A method for operating a device (such as a printer) having a first interface (such as USB interface) connectable to a first computer and a second interface (such as an Ethernet interface)...
7277969 Bus system design method, bus system, and device unit  
On the basis of a period of a timing signal, a signal propagation delay in a device unit, signal propagation delay in the timing signal bus and the data bus, and a setup time of another device...
7275171 Method and apparatus for programmable sampling clock edge selection  
A method and apparatus for transferring data across a clock domain boundary is described. In one embodiment, a fixed relationship between a faster clock and a slower clock is maintained in the...
7275174 Self-aligning data path converter for multiple clock systems  
A system and method for aligning an input signal (24) synchronized to a first clock signal (22) with a second clock signal (26) The invention includes a mechanism (106) for generating a third...
7272741 Hardware coordination of power management activities  
Systems and methods of managing power provide for receiving notification of a pending power state transition and using coordination hardware to determine whether the power state transition in a...
7272740 Performance indication system for use with a universal serial bus signal and a method of operation thereof  
A performance indication system for use with a Universal Serial Bus (USB) signal. In one embodiment, the performance indication system includes a rate discrimination subsystem that is configured...
7260735 Method and system for maintaining a running count of events updated by two asynchronous processes  
A method of maintaining a count of active events of a process is provided by a start counter and a complete counter. The start counter maintains a first count of start events and may be operated...
7257726 Circuit for generating wait signal in semiconductor device  
The present invention discloses a circuit for generating a wait signal in a semiconductor device. Even if an address input enable signal is synchronized with a clock and continuously or...