Match Document Document Title
7873858 Clock signal generation device and method  
A clock signal generator for a USB device. The clock signal generator includes a control circuit and a clock generator that does not need to include a crystal oscillator. The control circuit...
7873857 Multi-component module fly-by output alignment arrangement and method  
A method and multi-component electronic module device are provided that control the timing of output of data from a plurality of components on the multi-component module. One or more of the...
7865759 Programmable clock control architecture for at-speed testing  
According to one exemplary embodiment, an N-stage programmable clock control architecture includes N flip-flops, where the N flip-flops are clocked by a primary clock source, such as a PLL. The...
7865755 Clock frequency variation of a clocked current consumer  
A frequency regulator for varying a clock frequency of a power-supplied consumer operated in a clocked manner, wherein the frequency regulator is implemented to perform an overall variation of the...
7865709 Computer motherboard  
The present invention discloses a computer motherboard, which comprises: at least one memory module slot, a flash memory, a central processing unit socket; wherein, the memory module slot is used...
7865757 Capacity on demand using signaling bus control  
An apparatus and method is disclosed for providing capacity on demand using control to alter latency and/or bandwidth on a signaling bus in a computer system. If additional capacity is required,...
7855581 Real time clock monitoring method and system  
Method for monitoring a real time clock and a device having real time clock monitoring capabilities, the device includes: (i) a real time clock tree, (ii) a clock frequency monitor that is adapted...
7853819 Method and device for clock changeover in a multi-processor system  
A unit and method for clock changeover in a system having at least two processing units, in which switchover device(s) are provided by which a switchover between at least two operating modes of...
7849349 Reduced-delay clocked logic  
Delay in a clocked logic circuit is reduced by partially determining a next state of the clocked logic circuit based on a current state of the clocked logic circuit during a first portion of a...
7844849 System and method for identifying and manipulating logic analyzer data from multiple clock domains  
A system and method for identifying and manipulating logic analyzer data from multiple clock domains is presented. A logic analyzer receives debug data and determines whether the debug data is a...
7840864 Functional frequency testing of integrated circuits  
A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan...
7840863 Functional frequency testing of integrated circuits  
A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan...
7831049 Enhanced encryption method and system for ultra secure applications  
Techniques to bolster the security of an AlphaEta cryptosystem using spectral phase encoding. In one aspect, a spatial light modulator (SLM) is used to change the spectral code (spectral phase) of...
7831853 Circuit comprising mutually asynchronous circuit modules  
A circuit is described comprising a first (10) and a second circuit module (20) and a synchronization module (30). The first and the second module are mutually asynchronous, and are coupled by the...
7830923 Interval centroid based watermark decoder  
An interval centroid-based watermark encoder encodes a watermark into a packet flow. Intervals are defined for the packet flow. Some of the intervals are selected as group A intervals while other...
7827433 Time-multiplexed routing for reducing pipelining registers  
Serializing circuitry is provided that can multiplex multiple device output signals and that can drive time-multiplexed data signals on the bus wires of a data path of an electronic system. Bus...
7827431 Memory card having memory device and host apparatus accessing memory card  
A memory card includes a clock I/O circuit, a data I/O circuit, a delay element, and an adjustment value holding circuit. The clock input/output circuit receives a first clock from a host...
7818528 System and method for asynchronous clock regeneration  
The present invention is a method of asynchronous clock regeneration. The method includes synchronizing a first write pointer and a second write pointer, the first write pointer being an offline...
7818549 Event driven digital signal processor with time constraints  
The present invention relates to an event driven digital signal processor 1 comprising: a central arithmetical unit 5, a register 4, a controller 3, an instruction memory 2, and input/output...
7818603 Deriving accurate media position information  
Various embodiments utilize different counters or clocks, working in concert, to smooth out position information that is derived for a rendering/capturing device. Specifically, in at least some...
7809973 Spread spectrum clock for USB  
A method, apparatus or system for generating a clock signal that includes determining a transmission frequency within a first frequency range for receiving or transmitting a data stream, locking a...
7809974 Circuit to reduce power supply fluctuations in high frequency/high power circuits  
A circuit for transitioning clocking speeds, or frequencies, is provided. With this circuit, a clocking circuit providing a first clock signal at a first clock frequency is coupled to a counter. A...
7805627 Clock synchronization scheme for deskewing operations in a data interface  
A technique includes providing transmitters that are each associated with a data bit line of a bus, and each transmitter is clocked by an associated transmit clock signal. The technique includes...
7805628 High resolution clock signal generator  
A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period Tp to produce pulses of the clock signal. The first...
7802124 Microcode configurable frequency clock  
A microcode configurable frequency clock that may be used to control the speed of high speed comparison in an operational optical transceiver. The frequency clock includes a memory and a logic...
RE41752 Bus clock controlling apparatus and method  
The present invention relates to an apparatus and method for throttling a clock of a bus used for data exchange between devices in a computer such as a portable computer or notebook. Methods...
7797593 Method and apparatus for memory AC timing measurement  
A timing measurement circuit inside a memory chip delays balanced test signals for generating delayed test signals. Each of the delayed test signals is input a corresponding input pin of a memory...
7793134 Information processing apparatus working at variable operating frequency  
An information processing apparatus includes a clock signal generator unit that generates a clock signal which is variable in frequency. The information processing apparatus also includes a timing...
7792026 Method of calculating a time period to wait for missing data packets  
A method of receiving data packets. In the method of receiving data packets, a determination is made as to whether a received data packet is received out of an expected order. If the determining...
7772909 Supplying power to, and clocking, clocked loads  
A supply power can be fed in at a circuit arrangement for supplying power to, and clocking, clocked loads. The circuit arrangement provides a clock signal at a frequency and a supply voltage, the...
7774635 Multi-processing system distributing workload optimally during operation  
A multi-processing system includes: a selecting unit that selects a clock frequency for each processor chips based on lot-to-lot variation thereof; a calculating unit that calculates chip...
7764135 Pulse shaping circuit for crystal oscillator  
A circuit arrangement and method utilize a variable threshold, multi-stage pulse shaping circuit to pulse shape a signal output by a crystal oscillator circuit. Each stage of the pulse shaping...
7765315 Time synchronization of multiple time-based data streams with independent clocks  
Techniques are described for synchronizing multiple time-based data streams with independent clocks wherein relationships between clock rates of timing devices associated with the time-based data...
7761728 Apparatus, system, and method for resetting an inter-integrated circuit data line with a clock line  
An apparatus, system, and method are disclosed for resetting an inter-integrated circuit data line with a clock line. A hang module detects that a data line that carries data between an I2C bus...
7752480 System and method for switching digital circuit clock net driver without losing clock pulses  
A system and method for switching digital circuit clock net driver without losing clock pulses is presented. A device uses glitchless clock selection logic, which includes an edge detector, to...
7752477 Signal processor and method for processing a signal  
A signal processor includes a reference clock generator configured to generate a reference clock as a synchronization reference for a signal processing. A counter is configured to count the...
7752476 Fast transition from low-speed mode to high-speed mode in high-speed interfaces  
Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable,...
7739440 ATA HDD interface for personal media player with increased data transfer throughput  
This invention is a method allowing for interfacing high speed hard disk drives (ATA-HDD) in high throughput PIO modes to currently available digital media processors (DMP). The prescribed...
7739536 Intelligent frequency and voltage margining  
A system and method for voltage and frequency margining of a digital system such as a digital processing system. Various implementations of the present invention may be utilized to...
7739537 Multiple clock domain microprocessor  
A multiple clock domain (MCD) microarchitecture uses a globally-asynchronous, locally-synchronous (GALS) clocking style. In an MCD microprocessor each functional block operates with a separately...
7725755 Self-compensating delay chain for multiple-date-rate interfaces  
Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock...
7725757 Method and system for fast frequency switch for a power throttle in an integrated device  
In one embodiment, the present invention includes a counter to count core clocks, where the counter has a value to be incremented from zero to one less than a first bus ratio. Coupled to the...
7725754 Dual clock interface for an integrated circuit  
A dual clock interface for an integrated circuit is described. An integrated circuit includes interface circuitry. The interface circuitry has a hardwired logic block. The hardwired logic block...
7725759 System and method of managing clock speed in an electronic device  
A method of controlling a clock frequency is disclosed and includes monitoring a plurality of master devices that are coupled to a bus within a system. The method also includes receiving an input...
7725756 Method for generating programmable data rate from a single clock  
A method for generating a wide range of clock rates from a single clock. A delta is generated from a first clock signal and a second clock signal. An accumulative offset is generated from adding...
7721030 Method and device for connecting sensors or actuators to a bus system  
A method for connecting at least one sensor or actuator to a time-controlled bus system, the sensor or actuator carrying out a signal processing in at least two phases, the signal processing in a...
7719996 Encoding timestamps  
A logging system comprising counting logic adapted to generate a raw timestamp. The system further comprises encoding logic coupled to the counting logic and adapted to insert a group of bits of...
7716510 Timing synchronization circuit with loop counter  
An apparatus for synchronizing an output clock signal with an input clock signal includes a first timing synchronization circuit, control logic, and a counter. The first timing synchronization...
7710320 System and method for position determination by impulse radio  
A method for producing a first time base for a first ultra wideband radio obtains a time reference signal and phase locks a clock signal to the time reference signal The clock signal is counted...
7711975 Universal serial bus adaptive signal rate  
In some embodiments it is determined if a speed of a Universal Serial Bus cable of greater than 480 Mb per second is supported at each end of the Universal Serial Bus cable, the length of the...